1. Birds Eye View of Interconnection Networks
The Power of Topology
The Effect of Network
The Grace of Solution

2. Glimpse at Interconnection Networks

3. Seas for Networks
A wide variety of direct interconnection networks have been proposed for, or used in, parallel computers
They differ in topological, performance, robustness, and reliability attributes.

4. Classification: Static vs. Dynamic
Static or Direct
Ring
Mesh
Hypercube
………
Dynamic or Indirect:
Bus,
Crossbar,
MIN
000
001
100
110
111
011
010
101 P1 P2 P3 M1 M2 M3

5. Line, Ring and Fully Connected
Linear Array: the simplest topology. Fully Connected: Direct connection between every pair of processors, Highest cost, Similar to crossbar in some properties. Ring: Each node in the ring is connected to only two other nodes.Chordal Ring: A compromise between Ring and Fully Connected Network.

6. Mesh and Torus
Mesh Topology
2D Torus
3D Torus
Why mesh or Torus: 1) make full use of boundary link; 2) Node/edge Symmetry.
Is there any other wraparound approach? Read my Midimew Papers.
What is the diameter of torus, in comparison with meish?
How to layout the torus? Or a ring?
2D torus: Meshes with ``wraparound'' connections, e.g. the node at the top of the grid has an ``up'' link that connects to the node at the bottom of the grid (also left to right).

7. Hypercube
From 2-dimentional to 3-dimensional or even higher-dimensional.

8. Tree and Star
Tree and Star

9. Fat Tree four paths 8 port 4 port
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PE16
All 8 PEs on the left half(subtree) have a path to the Pes on the right half
Note that a message going from PE2 to PE5 may choose any one of four paths from the lower left router to the one at the root. This means that all four PE's attached to the lower left router have a path available to them to reach another node.

10. Crossbar switch Crossbar switch
P0 –> M1
P1 –> M3
P2 –> M2
P3 –> M0
Crossbar switch
On the other end of the spectrum is bus topology.
Cheapest,
but poorest in performance.
So again, we have to make compromise/trade off between cost and performance. We therefore have multistage.
N*N switches (N processors N memory modules). The switch configures itself dynamically to connect a processor to a memory module. No contention -- Supports N! permutations. Costly, hard to scale, wastes switches for most patterns.

11. Multistage Network : Omega Network
p processors and log2 p stages
Each stage consists of a perfect shuffle

12. Multistage Network : Butterfly
ButterFly Network