1. SVT- Status Update on R&D activities for TDR
IX SuperB General Meeting Workshop
Perugia - June 16-19, 2009
Giuliana Rizzo
Universita’ & INFN Pisa
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

2. SVT Status – SuperB Workshop, Perugia June 19 - 2009
SVT toward the TDR
Need to demonstrate:
we are able to built a Layer0 with the right specs for SuperB
we have a solid technical design for
external layers with double sided silicon strip
SVT support structure
Requirements set by performance and background studies:
Radius~ 1.5 cm , pitch 50 um, minimal material (~1% X/X0)
Back. Rate several MHz/cm2
Thin pixels, (striplets)
Optimization of the layout for SuperB physics and the new IR conditions (extended angular coverage, different radii)
First requirements could in principle be achieved with mature technology (dssd as in babar) BUT the high lumi beackground in SuperB impose to adopt thin pixels
Need to allow an easy access to IR for replacement of the Layer0 & beam pipe.
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

3. SVT Status – SuperB Workshop, Perugia June 19 - 2009
Layer0 baseline option
R&D work reorganized to prepare a baseline for TDR with:
Layer0 based on hybrid pixels:
Better chance (w.r.t to newer technologies) to meet the Layer0 requirements for the TDR timescale
Some R&D still required
Layer0 pixel options under study
Hybrid Pixels
CMOS DNW MAPS
Lower material & improved performance
Continue R&D on thin pixels technology
(SLIM5VIPIX Collaboration-INFN)
CMOS DNW MAPS + Vertical Integration technology very promising for Layer 0 but not yet mature for TDR timescale.
First DNW MAPS chip realized with two thin CMOS layers interconnected  first results by end of 2009
 if positive could be seriously considered for Layer0 performance improvement
Sensor
Digital tier
Analog tier
Wafer bonding & electrical interconn.
Pixels with Vertical Integration
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

4. SVT Status – SuperB Workshop, Perugia June 19 - 2009
Layer0 Module Specs
Key issues to demonstrate we can built it:
Front-end chip for high resistivity pixels
Multichip pixel module interfaces
Light Module support and cooling
Link
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

5. Hybrid Pixel front-end (I)
Hybrid Pixels
Hybrid Pixel front-end (I)
Produce & test a prototype front-end chip for high resistivity pixels with 50x50 um2 pitch & fast enough readout (background hit rate requires ~ 100 MHz/cm2)
Chip layout is starting: submission end of Sept. ’09 with (ST 130 nm process). Pixel sensor and chip interconnected by bump-bonding in spring 2010  testbeam in Sept
Analog design of the front-end ongoing
G. Traversi (Bergamo/PV)
S/N ~ 100 for 200 um thick sensor
Preliminary
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

6. Hybrid Pixel front-end (II)
Fast data push readout architecture already developed & deployed successfully on MAPS chip
Now optimized for Hybrid Pixel with target rate 100 MHz/cm2 on full chip size (~1.3 cm2)
Efficiency > 60MHz Rdclk on matrix
Need ~ 160 MHz clock on the parallel output bus
VHDL simulation results-F.Giorgi (Bologna)
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

7. Pixel Module Interfaces (I)
M. Citterio (Milano)
Light material (Al/Kapton) high speed (160 MHz) and high track density pixel bus (requirements in competition!)
Will be CERN shop
Simulation with present design encouraging
Several options under evaluation for the link HDI- DAQ board
Fast (3<->20Gbit/s) & “rad hard” link ( depending on the location)
Mixed technology solution affordable with 3 Gbit/s:
storing data on the HDI (glue logic - L1 time buffer – serializer)
Cu link HDI  transition card
optical link in medium rad. tolerant area: transition card  DAQ
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

8. Pixel Module Interfaces (II)
M. Citterio (Milano)
Prototype Al bus
HDI based on FPGA for the TDR phase, later need to implement it on ASICS rad tolerant)
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

9. Light pixel module support & cooling
M.Massa-F.Bosi (Pisa)
Light support with integrated cooling needed for pixel module (P=2W/cm2)
Carbon Fiber support with integrated microchannel with coolant fluid developed:
Total support/cooling thickness = 0.28 % X0
First thermo-hydraulic measurements on prototypes under way
12.8 mm
700 mm
Working on options for material reduction
 0.2 % X0
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

10. Radiation tolerance of DNW MAPS
L. Ratti (Pavia)
Irradiation with 60Co g-ray up to ~ 10 Mrad
Gain reduction ~ 3%/Mrad
Noise increase ~ 15%/Mrad
Significant recovery after 100ºC/168h annealing cycle
Noise increase ~ 10 Mrad
Charge collection efficiency under test
Next step investigate bulk damage
Apsel3T1 test chip (tp=200, 400 ns)
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

11. SVT Geometry Optimization with FastSim
Several studies shown in DGWG & FastSim sessions (N.Neri, G.Simi, J. Walsh, M. Bomben)
Preliminary conclusions on internal SVT geometry:
To improve tracking performance better to reduce the inner radius of the DCH instead of increasing the SVT outer radius.
Expanding the SVT doesn’t improve errors on time dependent measurement in channels with Ks
Probably the SVT strip layers will be at the current BaBar SVT radii.
Module design is starting with this hypothesis (FE chip evaluation and mechanical design)
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

12. SVT Status – SuperB Workshop, Perugia June 19 - 2009
SVT Mechanics (I)
F. Bosi (Pisa)
M.Sullivan I.R. model with L0 positioned
Need to start
Good progress
Brainstorming phase
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

13. SVT Status – SuperB Workshop, Perugia June 19 - 2009
SVT Mechanics (II)
F. Bosi (Pisa)
I.R. Model+L0
M.Sullivan I.R. model with L0 positioned
Very fruitful discussion with the IR designers on the main issue: easy/fast access for replacement of the Layer0 & beam pipe.
Layer0 upgrade & beam pipe at smaller radius
Brainstorming on various options
Fast removal of the entire IR beam pipe +Layer0+SVT inserting a sliding temporary Support Tube with rails for the access
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

14. SVT Status – SuperB Workshop, Perugia June 19 - 2009
Background Update
E.Paoloni (Pisa)
New numbers from the nastier luminosity background (e+e- pair production): rate is definitely too high with present radial configuration bp+L0
Rate become acceptable moving the beam pipe to 1.5 cm radius … just above the present Layer0 minimum radius
We can handle a beam pipe/Layer0 radius where the back. rate is ~ 20 MHz/cm2. With a x5 safety  100 MHz/cm2 ( ~ OK for readout chip)
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

15. SVT Status – SuperB Workshop, Perugia June 19 - 2009
Conclusions
SVT work reorganized to demonstrate for the TDR timescale that we will be able to built a baseline SVT Layer0 +L1-L5 based on hybrid pixels + silicon strip
R&D is proceeding well in the most critical areas (Layer0) and simulation results are encouraging
Production of various components underway to have real measurements for the TDR ...no too much contingency though.
Engineering of the more “standard” part of the detector still to start (L1-L5 & support structure): getting organized with a quite little manpower.
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

16. SVT Status – SuperB Workshop, Perugia June 19 - 2009
backup
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

17. Agenda of the SVT Parallels
Tuesday 16 June 16-17:30
Introduction – G. Rizzo
SVT Backgrounds - Present knowledge E. Paoloni (Pisa)
Front-end analog cell optimization for hybrid pixel sensors – G. Traversi (Bergamo/Pavia)
Wednesday 17 June 9-10:30
Radiation Damage Studies on DNW MAPS – L. Ratti (Pavia)
Vertical Integration Activities – L. Ratti (Pavia)
Pixel Readout Architecture Optimization - Simulation Results - F. Giorgi (Bologna)
Wednesday 17 June 11-12:30
Pixel Module Interfaces – M. Citterio (Milano)
SVT Mechanics – F. Bosi (Pisa)
Layer0 support & cooling - M. Massa (Pisa)
Discussion
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

18. SVT Status – SuperB Workshop, Perugia June 19 - 2009
Background Update
E.Paoloni (Pisa)
New numbers from the nastier luminosity background (e+e- pair production): rate is definitely too high with present radial configuration bp+L0
Rate become acceptable moving the beam pipe to 1.5 cm radius … just above the present Layer0 minimum radius
We can handle a beam pipe/Layer0 radius where the back. rate is ~ 20 MHz/cm2. With a x5 safety  100 MHz/cm2 ( ~ OK for readout chip)
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

19. SVT baseline configuration
40 cm
30 cm
20 cm
Layer0
Layer 0: Hybrid Pixels
Radius~1.5 cm, Module length~10 cm
Power consumption ~ 2 W/cm2 in the active area
Total material budget ~ 1% X0
Si sensor + FE chips % X0
Al Bus + SMD comp % X0
Support & cooling ~ 0.3% X0
Layer Radius cm cm cm cm
to 12.7 cm
to 14.6 cm
SuperB Interaction Region Schematic SVT superimposed
CF Support with microchannels technology is within specs with material ~ 0.3% X0
External Layers: Baseline similar to the present BaBar SVT: double sided silicon detectors 300 um thick
Assume same BaBar radii for the 5 layers
L1-L2-L3 barrel shape
L4-L5 arch shape
Extend coverage down to 300 mrad FW and BW
In BaBar it was 300 mrad FW and 520 mrad BW
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

20. SVT Status – SuperB Workshop, Perugia June 19 - 2009
SVT SW related studies
Background Studies – News in the next talk by E. Paoloni
Implementation of the SVT baseline in FastSim and first performance results will be presented in other parallel session:
Wednesday 17 June 2009
14:00->15:30    Parallel - Tracking (DGWG)
Tracking Performance with the
SVT baseline configuration - N. Neri
Boost sensitivity on time dependent measurements - N. Neri
16:00->17:30   Parallel - Fast Simulation
Resolution model for pixels with digital readout - J. Walsh
SVT passive material implementation in FastSim - M. Bomben
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

21. SVT Group Organization & Update
Regular SVT bi-weekly meeting for TDR started in April. (Tue– 17:15 CET)
WBS and TDR work schedule prepared. Preliminary outcome in the next slides.
SVT – management structure (responsibility for TDR preparation)
G. Rizzo
SVT Status – SuperB Workshop, Perugia June

22. Layer 0 pixel R&D activities
1. Hybrid Pixels:
- Sept 2009 produce small prototype Front-End chip for hybrid pixel:
50x50 um pitch, 32x 128 pixel matrix, STMicroelectronics 130 nm
same readout architecture data push developed for MAPS with optimization:
Simulation for full size matrix (256x180 pixels) should have readout efficiency ~ 98% with 100 MHz/cm2 hit rate
reoptimize analog cell (small capacitance ~ fF, high signal from MIP with fully depleted 200 um substrate)
significant reduction in the analog power consumption w.r.t MAPS chip ~ 1 uA/pixel (?)
Power consumption for digital section dominates ~ 1W/cm2
- Sept 2009 produce pixel sensors (ITC, IRST)
- Test with beam Sept 2010: pixel sensor bump bonded to the FE chip.
Bump bonding could be an issue since we will not have the full wafer for the FE chips.
2. Develop Pixel module components, hybrid pixel & MAPS (next slide)
3. Continue R&D on MAPS:
- Large Matrix (APSEL5D~40 mm2 active area) in production beginning of 2010
- Radiation damage studies (Co60 up to 5 Mrad, Neutron irradiation to start)
- Testbeam on APSEL5D in Sept. 2010, single chip (no time for MAPS mod. integration).
- Later testbeam (post TDR with MAPS module)
At the time of the TDR report on progress on MAPS, possible option for performance improvements. Design Layer0 easily accessible for replacement
G. Rizzo
SVT Status – SuperB Workshop, Perugia June