1. Reading and writing to data memoryrs
Imm
Lw rt Imm(rs) 5 16
Register
file
Sign extend
Offset 32
Base address +
Data address to data memory

2. Reading and writing to data memory
Lb rt Imm(rs)
Address (32 bits)
Data (8 bits)
Data memory
Sign extension
Lbu: Zero extend
There are also Lh and Lhu

3. Reading and writing to data memory
Sw rt Imm(rs)
Sh rt Imm(rs)
Sb rt Imm(rs)
Remember: Alignment for Sw and Sh

4. Read and write from/ to the data memory
Lw rt Imm(rs) Sw rt Imm(rs)
Lh rt Imm(rs) Sh rt Imm(rs)
Lhu rt Imm(rs)
Lb rt Imm(rs) Sb rt Imm(rs)
Lbu rt Imm(rs)

5. Zero ext.
Branch
logic A
ALU 4 B + 31 +
Sgn/Ze
extend
Lw rt Imm(rs)

6. Zero ext.
Branch
logic A
ALU 4 B + 31 +
Sgn/Ze
extend
Lw rt Imm(rs)

7. Lw rt Imm(rs) Read Data Zero ext. Branch logic A ALU 4 B + 31 + Sgn/ZeA
ALU 4 B + 31 +
Sgn/Ze
extend
Lw rt Imm(rs)
Read Data

8. Lw rt Imm(rs) … next instr
Zero ext.
Branch
logic A
ALU 4 B + 31 +
Sgn/Ze
extend
Lw rt Imm(rs)
… next instr

9. Zero ext.
Branch
logic A
ALU 4 B + 31 +
Sgn/Ze
extend
Sw rt Imm(rs)

10. Sw rt Imm(rs) Write Data
Zero ext.
Branch
logic A
ALU 4 B + 31 +
Sgn/Ze
extend
Sw rt Imm(rs)
Write Data