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Off-path Leakage Power Aware Routing for SRAM-based FPGAs

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Presentation on theme: "Off-path Leakage Power Aware Routing for SRAM-based FPGAs"— Presentation transcript:

1 Off-path Leakage Power Aware Routing for SRAM-based FPGAs
Keheng Huang, Yu Hu, Xiaowei Li Institute of Computing Technology, Chinese Academy of Sciences. Bo Liu, Hongjin Liu, Jian Gong Beijing Institute of Control Engineering.

2 Outline Leakage power in FPGAs On-path leakage power
Off-path leakage power corresponds to SHD Space of SHD reduction: Probability skew Propose an SHD guided Off-path leakage aware routing Experimental validation 11-Apr-19 Keheng Huang/ ICT, CAS

3 Outline Background Leakage power in FPGAs On-path leakage power
Off-path leakage power corresponds to SHD Space of SHD reduction: Probability skew Propose an SHD guided Off-path leakage aware routing Experimental validation 11-Apr-19 Keheng Huang/ ICT, CAS

4 Background Architecture of SRAM-based FPGA CLB LUT Switch box MUX
Wire segment 11-Apr-19 Keheng Huang/ ICT, CAS

5 Background Leakage power in SRAM-based FPGA
used part: Active leakage power unused part: Sleep leakage power Routing resources: 60%-70% leakage power 11-Apr-19 Keheng Huang/ ICT, CAS

6 Background Architecture of MUX On-path On-path input
On-path transistor Off-path Off-path inputs Off-path transistors 11-Apr-19 Keheng Huang/ ICT, CAS

7 Background Related work
Configuration bits inversion [Anderson, TCAD’06] Don’t take the logic state of off-path inputs into consideration! J. Anderson, F. Najm, “Active Leakage Power Optimization for FPGAs,” TCAD, Mar, 2006, pp 11-Apr-19 Keheng Huang/ ICT, CAS

8 Outline Key Observation Leakage power in FPGAs On-path leakage power
Off-path leakage power corresponds to SHD Space of SHD reduction: Probability skew Propose an SHD guided Off-path leakage aware routing Experimental validation 11-Apr-19 Keheng Huang/ ICT, CAS

9 Key observation Off-path leakage take up most of the leakage power in a multiplexer SPICE simulation 110C 65nm PTM Off-path leakage 80.59% 11-Apr-19 Keheng Huang/ ICT, CAS

10 Key observation Off-path leakage power corresponds to the logic state of inputs On-path input Off-path inputs Smallest leakage 0000,1111 largest leakage 0111,1000 No voltage difference Voltage difference 11-Apr-19 Keheng Huang/ ICT, CAS

11 Key observation Metric: State Hamming Distance (SHD)
Take 0111 as an example The leakage power of a multiplexer is optimized if the average SHD for all input vectors of the multiplexer is minimized 11-Apr-19 Keheng Huang/ ICT, CAS

12 Key observation Best case
The prob. of each wire to be logic 1, denoted as P(1) The space of SHD reduction SHD1=3 SHD2=0 Best case 11-Apr-19 Keheng Huang/ ICT, CAS

13 Key observation Worst case
The prob. of each wire to be logic 1, denoted as P(1) The space of SHD reduction SHD1=SHD2 Worst case 11-Apr-19 Keheng Huang/ ICT, CAS

14 Key observation The prob. of each wire to be logic 1, denoted as P(1)
The space of SHD reduction Probability skew How far P(1) is away from 0.5 11-Apr-19 Keheng Huang/ ICT, CAS

15 Key observation Optimization space is affected by probability skew of each circuit Activity estimator tool (ACE) [Choy] Average probability skew=0.37 Huge space for off-path leakage power optimization N. C. K. Choy, “Power Modeling for FPGAs.” in 11-Apr-19 Keheng Huang/ ICT, CAS

16 Outline Proposed algorithm Leakage power in FPGAs
On-path leakage power Off-path leakage power corresponds to SHD Space of SHD reduction: Probability skew Propose an SHD guided Off-path leakage aware routing Proposed algorithm Experimental validation 11-Apr-19 Keheng Huang/ ICT, CAS

17 Off-path leakage power aware routing
Step 1 Establishing leakage aware routing graph Step 2 Leakage power estimation Step 3 Off-path leakage aware routing 11-Apr-19 Keheng Huang/ ICT, CAS

18 Off-path leakage power aware routing
Step 1 Establishing leakage aware routing graph Connections among wire segments Logic state probability (ACE) Objective Estimate leakage power Guide leakage power optimization 11-Apr-19 Keheng Huang/ ICT, CAS

19 Off-path leakage power aware routing
Step 2 Leakage power estimation where P(SHDv) is the probability of each SHD state L(SHDv) is the leakage power for each SHD state SPICE simulation 11-Apr-19 Keheng Huang/ ICT, CAS

20 Off-path leakage power aware routing
Example of Step 2 P(SHDv) L(SHDv) SPICE simulation LMUX 11-Apr-19 Keheng Huang/ ICT, CAS

21 Off-path leakage power aware routing
Step 3 Off-path leakage aware routing Original router(timing and congestion) Off-path leakage aware router 11-Apr-19 Keheng Huang/ ICT, CAS

22 Off-path leakage power aware routing
Example of Step 3 Original routing Optimized result 1 Minimize the number of off-path transistors Leakage=181.12nw Leakage=4.0nw 11-Apr-19 Keheng Huang/ ICT, CAS

23 Off-path leakage power aware routing
Example of Step 3 Original routing Optimized result 2 Reduce the gap of P(1)s Leakage=181.12nw Leakage=62.76nw 11-Apr-19 Keheng Huang/ ICT, CAS

24 Outline Experimental results Leakage power in FPGAs
On-path leakage power Off-path leakage power corresponds to SHD Space of SHD reduction: Probability skew Propose an SHD guided Off-path leakage aware routing Experimental results Experimental validation 11-Apr-19 Keheng Huang/ ICT, CAS

25 Virtex-like routing resources:
Experimental results MCNC Benchmark set Berkeley ABC mapper Virtex-like routing resources: Single (8%), double(20%), hex(60%), and long(12%) Gate-level netlist VPR: Academic FPGA placement and routing tool Implemented design 11-Apr-19 Keheng Huang/ ICT, CAS

26 Experimental results Phase 1 Comparison of active leakage power
Comparison of critical-path delay Phase 3 Comparison of total wire length Phase 4 Comparison of dynamic power 11-Apr-19 Keheng Huang/ ICT, CAS

27 Experimental results Phase 1 Comparison of active leakage power
11-Apr-19 Keheng Huang/ ICT, CAS

28 Experimental results Phase 2 Comparison of critical-path delay
Reported by placement and routing tool VPR 11-Apr-19 Keheng Huang/ ICT, CAS

29 Experimental results Phase 3 Comparison of total wire length
Analyzing the implemented design 11-Apr-19 Keheng Huang/ ICT, CAS

30 Experimental results Phase 4 Comparison of dynamic power
1.1nw Leakage power: 1.6*106nw 11-Apr-19 Keheng Huang/ ICT, CAS

31 Conclusion Observe the off-path leakage take up most of the active leakage power Off-path leakage strongly depends on the SHD of the multiplexer Propose an off-path leakage power aware routing algorithm Experimental validation Reduce active leakage power by 17% Increase area and performance overhead by 1% and 3% 11-Apr-19 Keheng Huang/ ICT, CAS

32 Thank you for your attention
Questions? 11-Apr-19 Keheng Huang/ ICT, CAS

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