1. RTL Design Methodology
Lecture 11
RTL Design Methodology
Part I:
STATISTICS Example

2. Structure of a Typical Digital System
Data Inputs
Control Inputs
Control
Signals
Datapath
(Execution
Unit)
Controller
(Control
Unit)
Status
Signals
Data Outputs
Control Outputs

3. Hardware Design with RTL VHDL
Interface
Pseudocode
Datapath
Controller
Block
diagram
Block
diagram
State diagram
or ASM chart
VHDL code
VHDL code
VHDL code

4. Steps of the Design Process
Text description
Interface
Pseudocode
Block diagram of the Datapath
Interface divided into Datapath and Controller
ASM chart of the Controller
RTL VHDL code of the Datapath, Controller, and Top-Level Unit
Testbench for the Datapath, Controller, and Top-Level Unit
Functional simulation and debugging
Synthesis and post-synthesis simulation
Implementation and timing simulation
Experimental testing using FPGA board

5. Steps of the Design Process Introduced in Class Today
Text description
Interface
Pseudocode
Block diagram of the Datapath
Interface divided into Datapath and Controller
ASM chart of the Controller
RTL VHDL code of the Datapath, Controller, and Top-level Unit
Testbench for the Datapath, Controller, and Top-Level Unit
Functional simulation and debugging
Synthesis and post-synthesis simulation
Implementation and timing simulation
Experimental testing using FPGA board

6. Class Exercise 1
STATISTICS

7. Pseudocode no_1 = no_2 = no_3 = sum = 0 wait for go for i=0 to k-1 do
sum = sum + din
if din > no_1 then
no_3 = no_2
no_2 = no_1
no_1 = din
elseif (din > no_2) then
no_2 = din
elseif (din > no_3) then
no_3 = din
end if
end for
avr = sum / k

8. Circuit Interface n 2
clk
reset
din go
done
dout
dout_mode
Statistics

9. Interface Table Port Width Meaning clk 1 System clock. reset
System reset.
din n
Input Data. go
Control signal indicating that the first input is ready. Active for one clock cycle.
done
Signal set to high after the output is ready.
dout
Output dependent on the dout_mode input.
dout_mode 2
Control signal determining value available at the output.
00: avr, 01: no_1, 10: no_2, 11: no_3.

10. STATISTICS:
Solutions

11. Block diagram of the Datapath
din n n n
en1 en
reset
rst
n+m
clk
clk A
gt1
n+m
no_1
A>B n
esum en
reset n B
rst
clk
clk 1 s2
sum
n+m
en2
enc en
reset en
reset
rst
rst
clk
clk
clk
clk A
gt2
no_2 m
A>B
n+m n n B i 1 s3
>> m
= k-1
en3 en
reset
rst n
clk
clk A
gt3
avr
A>B n
no_3 zi
no_1
no_2
no_3 B n n n
dout_mode 00 01 10 11 2 n
dout
Block diagram of the Datapath

12. Interface with the division into the Datapath and Controller
dout_mode
din
clk
reset go n 2
gt1
gt2
gt3
Datapath
Controller zi
en1
en2
en3
esum
enc s2 s3 n
dout
done

13. ASM Chart of the Controller