1. CSC3050 – Computer Architecture
Prof. Yeh-Ching Chung
School of Science and Engineering
Chinese University of Hong Kong, Shenzhen

2. Review: Major Components of a Computer

3. Review: Instruction Set Architecture (ISA)
The interface description separating the software and hardware
Instruction Set Architecture
Software
Hardware

4. Analog vs. Digital Analog Signal Digital Signal Example: audio, video
Vary in a smooth way over time
Analog data are continuously valued
Example: audio, video
Digital Signal
Maintains a constant level then changes to another constant level (generally operate in one of the two states)
Digital data are discretely valued
Example: computer data

5. Radix or Base
An ordered set of symbols, called digits, with relations defined for addition, subtraction, multiplication and division
Radix or base of the number system is the total number of digits allowed in the number system

6. Decimal, Binary, Octal and Hexadecimal
System Name
Decimal
Binary
Octal
Hexadecimal
Radix 10 2 8 16
0000 1
0001
0010 3
0011 4
0100 5
0101 6
0110 7
0111
1000 9
1001 11
1010 12 A
1011 13 B
1100 14 C
1101 15 D
1110 E
1111 17 F
10000 20

7. Number Systems Decimal numbers Binary numbers 1000’s column
five
thousands
three
hundreds
seven
tens
four
ones
8’s column
4’s column
2’s column
1’s column
one
eight
four
zero
two

8. Powers of Two
20 = 1
21 = 2
22 = 4
23 = 8
24 = 16
25 = 32
26 = 64
27 =128
28 = 256
29 = 512
210 = 1024
211 = 210 × 21 = 2048
212 = 210 × 22 = 4096
216 = = 65536 …
220 = 210 × 210 =
Handy to memorize up to 210

9. Decimal vs Binary Numbers
Binary to decimal conversion:
Convert to decimal
16×1 + 8×0 + 4×0 + 2×1 + 1×1 = 1910
Decimal to binary conversion:
Convert 4710 to binary
32×1 + 16×0 + 8×1 + 4×1 + 2×1 + 1×1 =
N-digit decimal number
How many values? 10N Range: [0, 10N−1]
Example: 3-digit decimal number:
103 = 1000 possible values Range: [000, 999]
N-digit binary number
How many values? 2N Range: [0, 2N−1]
Example: 3-digit binary number:
23 = 8 possible values Range: [0002, 1112]
[ 0 , 7 ]

10. Hexadecimal Numbers Hexadecimal to binary conversion
4AF16 (or 0x4AF)
Hexadecimal to decimal conversion
162× × ×15 =

11. Exercise L02-1 Ex 1: Convert 368 to binary
368=
3610=

12. Unsigned and Signed Numbers
Hexadecimal
Binary
Decimal (Unsigned)
Decimal (2’s Complement)
0x8F
127
0x8E
126 …
0x02 2
0x01 1
0x00
0xFF
28−1 = 255 −1
0xFE
254 −2
0x82
130
−126
0x81
129
−127
0x80
128
−128
Complement all bits
Then add 1
Complement all bits
Then add 1

13. Exercise L02-2
Ex 3: For a n-bit 2’s complement signed binary numeral system, what’s the largest positive number and the smallest negative number?

14. Digital Circuits Digital circuits generally contain two parts
Combinational logic
Sequential logic
Combinational circuits consist of logic gates with inputs and outputs
The outputs at any instance of time depend only on the combination of the input values based on logic operations such as AND, OR, etc.
Sequential circuits, in addition to inputs and outputs also have storage elements, therefore the output depends on both the current inputs as well as the stored values

15. Digital Signal Representation
Active High
High voltage activates/enables the pin
Active Low
Low voltage activates/enables the pin

16. Logic Levels

17. Logic Gates OR
NOR
AND
NAND
buffer
NOT (inverter)
XOR
XNOR

18. Exercise L02-3 Ex 4: What is the schematic view of a NOR gate?
368=
3610=

19. Truth Table
A tool for describing how the output of a logic circuit depends on the logic levels presented at the inputs
The number of input combinations will equal 2N for an N-input truth table
Inputs
Output A B Z 1
Logic Circuit A Z B

20. Exercise L02-4 Ex 5: Draw the truth table of a 3-input AND gate.
368=
3610=

21. Combinational Circuits
In combinational circuits, the output at any time is a direct function of the applied external inputs
Combinational Circuits …
Input X
Output Z
Z = F(X)

22. Design Procedure of Combinational Circuits
Circuit Specification
Truth Table
(How many input/output?)
Minimization
(K-maps, algebraic manipulation, CAD tools)
Logic Diagram

23. Exercise L02-5
Ex 6: Implement AB+CD using NAND gates only

24. Propagation Delay
The delay when the signal arrives at the input of a circuit, and when the output of the circuit changes, is called the propagation delay.
A circuit is considered to be fast, if its propagation delay is small (ideally as close to 0 as possible). X Z Y
Delay between input (X, Y) and change in output Z.

25. Timing Diagram The inputs to a circuit can be changed over time.
The timing diagram shows the values of the input signals to a circuit with the passage of time, in the form of a waveform.
It also shows a waveform for the output. X Y Z
Inputs
Output
Time
Propagation delay = τ

26. Fan-in Fan-in of a gate is the number of inputs to the gate.
For a 3-input OR gate, the fan-in = 3.
There is a limitation on the fan-in for any gate.
In CMOS IC technology, higher fan-in implies slower gates (higher propagation delays).

27. Fan-out
Fan-out is the number of gates that can be driven by a driver gate.
The driven gate is called the load gate.
There is a limit to the number of load gates that can be driven by a driver gate.
Fan-out = 3

28. Buffers
Buffers have a single input and a single output, where output = input.
Buffers help increase the driving capability of a circuit by increasing the fan-out.
Drive strength: how much load a gate can drive.
Greater drive strength, load gates are (dis)charged more quickly.

29. Decoders (1) Information is represented by binary codes.
Circuits that perform decoding are called decoders.
A decoder is a minterm generator.
Minterm: product that includes all input variables
ABC, ABC, ABC ̅ ̅ ̅

30. Decoders (2) N inputs, 2N outputs
One-hot outputs: only one output HIGH at once
Binary 2-to-4 Decoder
Note: “x” denotes don’t care.

31. Decoders (3)
2-to-4 Decoder Logic Diagram

32. Decoder Applications Decode 3-bit opcodes: Home automation: ADD SUB C0
AND
XOR
NOT
LOAD
STORE
JUMP C0 C1
Light
A/C
Door TV

33. Decoders as Binary Adder

34. Multiplexers
Directs one of 2n input to the output, basically a data selector.
Input to output direction is done based on a set of n select bits. …
2n-to-1 MUX
2n inputs
1 output
n select bits

35. Sequential Circuits Give sequence to events Have memory (short-term)
Use feedback from output to input to store information
The state of a circuit influences its future behavior
State elements store state
Latch
Flip-flop

36. Bistable Circuit Fundamental building block of other state elements
Two outputs: Q, Q
No inputs
Consider the two possible cases:
Q = 0: then Q = 1, Q = 0 (consistent)
Q = 1: then Q = 0, Q = 1 (consistent)
Stores 1 bit of state in the state variable, Q (or Q).
But there are no inputs to control the state. ̅ ̅ ̅ ̅

37. SR (Set/Reset) Latch SR Latch Consider the four possible cases:

38. SR Latch Analysis（1） S = 1, R = 0: S = 0, R = 1: then Q = 1 and Q = 0̅ ̅

39. SR Latch Analysis （2） S = 0, R = 0: S = 1, R = 1: then Q = Qprev
Memory
S = 1, R = 1:
then Q = 0, Q = 0
Invalid (Q = Q) ̅ ̅

40. SR Latch Symbol SR (Set/Reset) Latch
Stores one bit of state (Q)
Control what value is being stored with S, R inputs
Set: Make the output 1 (S = 1, R = 0, Q = 1)
Reset: Make the output 0 (S = 0, R = 1, Q = 0)
Must do something to avoid invalid state (when S = R = 1)

41. Gated D Latch Two inputs: CLK, D Function
CLK: controls when the output changes.
D (data input): controls what the output changes to.
Function
When CLK = 1, D passes through to Q (transparent).
When CLK = 0, Q holds its previous value (opaque).
Avoids invalid case when Q ≠ NOT Q. ̅

42. Gated D Latch Internal Circuit

43. Master-Slave D Flip-Flop
Two back-to-back latches (L1 and L2) controlled by complementary clocks.
When CLK = 0
L1 is transparent
L2 is opaque
D passes through to Y
When CLK = 1
L1 is opaque
L2 is transparent
Y passes through to Q
Thus, on the edge of the clock (when CLK rises from 01), D passes through to Q. Y

44. Edge-Triggered D Flip-Flop
Inputs: CLK, D
Function
Samples D on rising edge of CLK
When CLK rises from 0 to 1, D passes through to Q
Otherwise, Q holds its previous value
Q changes only on rising edge of CLK
Called edge-triggered.
Activated on the clock edge.

45. Latch and Flip-Flop Latch is level-sensitive.
Flip-flop is edge-triggered.

46. Registers
A register is a simple memory device that is composed of a series of flip-flops wired together so that they share a common clock pulse.
Registers come in various sizes and types.
The size of a register is closely tied to the structure of the microprocessor, e.g. 8-bit registers for microprocessor architecture with 8-bit wide data.

47. 4-Bit Register A simple 4-bit register can be made with 4 D-FF
Common Clock
At each positive-edge, 4 bits are loaded in parallel
Previous data is overwritten
Common Clear
Asynchronous clear
When Clear = 0, all FFs are cleared; i.e. 0 is stored.

48. Shift Registers
Serial-in, serial-out: A register which can shift its stored bits laterally in one or both directions is called a shift registers.
Common Clock
At each positive-edge, 4 bits are loaded in parallel
Previous data is overwritten
Which direction is this registering shifting?

49. Bidirectional Shift Register with Parallel Load