1. DRAM
Hwansoo Han

2. DRAM Organization
Cell
(1 bit)

3. Bus Transmission

4. Precharge & Row Access

5. Column Access

6. Data Transfer
Page mode enables overlap with CAS

7. Bus Transmission

8. DRAM Latency DRAM latency = A+B+C+D+E+F
A: Transaction request may be delayed in Queue
B: Transaction request set to memory controller
C: Transaction converted to command sequences (may be queued)
D: Commands sent to DRAM
E: Requires only a CAS, RAS+CAS or PRE+RAS+CAS
F: Transaction sent back to CPU

9. DRAM DIMMs Dual inline memory module (DIMM)
A PCB with 8 to 16 DRAM chips
All chips receive identical control and addresses
Data pins from all chips are directly connected to PCB pins
Advantages
A DIMM acts like a high capacity DRAM chip with a wide interface
8 chips with 8-bit interfaces to connect 64-bit memory bus
Easier to replace/add memory in a system
Disadvantage
Memory granularity problem
Can add by the unit of DIMM
Pay full price of DIMM, not
actual amount of increase needed

10. Memory Modules (DIMMs)
addr (row = i, col = j)
: supercell (i,j)
DRAM 0
64 MB
memory module
consisting of
eight 8Mx8 DRAMs
DRAM 7
bits
56-63
bits
48-55
bits
40-47
bits
32-39
bits
24-31
bits
16-23
bits
8-15
bits
0-7 31 7 8 15 16 23 24 32 63 39 40 47 48 55 56
64-bit doubleword at main memory address A
64-bit doubleword 31 7 8 15 16 23 24 32 63 39 40 47 48 55 56
64-bit doubleword at main memory address A
Memory
controller

11. DRAM Banks Banks Independent arrays within a chip advantages
Lower latency
Higher bandwidth by overlapping
Disadvantages
Banks area overhead
More complicated control
Common addressing scheme
Rank is the DIMM id
rank
row
bank
column
offset

12. Multiple Banks/Channels
How do they help?

13. SDRAM Synchronous DRAM Access control is synchronized to system clock
2 group of DIMMs to overlap precharge interval
Pipelined accesses
Mesh topology
Addr & cmd
Data bus
DIMM select

14. DRAM Evolution Overview
Throughput & Latency

15. DRAM Evolution (1)
Conventional DRAM

16. DRAM Evolution (2)
Fast Page Mode (FPM)

17. DRAM Evolution (3)
Extended Data Out (EDO)
+ Fast page mode

18. DRAM Evolution (4)
Burst EDO

19. DRAM Evolution (5)
Synchronous DRAM (SDRAM)

20. SDRAM Evolution ESDRAM DDR SDRAM DDR2 DDR3 SDRAM with a row cache
Allows starting next RAS to the same bank in parallel with current CAS
DDR SDRAM
Double data rate using both clock edges (double pumping)
DDR2
Higher frequency FSB than DDR
100/133/166/200 MHz vs. 200/266/333/400 MHz
Upto 3.2GB/s (PC-3200) vs. 6.4GB/s (PC2-6400) – 64bit FSB
Lower voltage DDR : 1.8v vs. 2.5v
More banks (to operate at higher frequency than DDR)
longer CAS delay (wider prefetch buffer than DDR, 4-bit vs 2-bit)
DDR3
400/533/667/800 Mhz FSB, 1.5v, 8-bit prefetch buffer

21. Summary DRAM organization DRAM evolution (enhance throughput)
2D matrix (RAS, CAS)
DRAM evolution (enhance throughput)
Fast page mode (FPM)
Extended data out (EDO)
Burst mode, page mode
Synchronous DRAM (SDRAM)
SDRAM evolution
Extended SDRAM (ESDRAM)
DDR, DDR2