1. Mark Bristow CENBD 452 Fall 2002
555 Timer – LM555CN
Mark Bristow
CENBD 452 Fall 2002

2. What is it and Why do I care?
Generates time delays
Can divide frequencies
Modulate Pulse widths
Operate as a linear ramp
Most importantly, can be implemented as a clock signal, in Astable Mode

3. Pin Diagram Pin 1 – Ground Pin 2 – Trigger Pin 3 – Output
Pin 4 – Reset
Pin 5 – Control Voltage
Pin 6 – Threshold
Pin 7 – Discharge
Pin 8 - +Vcc
Pin 1 - Ground
Self Explanatory
Pin 2 – Trigger
Used to trigger timing event in monostable mode
Pin3 – Output
The output signal of the chip
Typically 100nS switching times
Pin 4 – Reset
Asynchronous Active Low Reset
Pin 5 – Control Voltage
Used to control the output pulse width independent of the RC circuitry
Pin 6 – Threshold
Used to reset the output, active high at 2/3 V+ ( normal voltage on pin 5)
Allows for level sensitive waveforms
Pin 7 – Discharge
Allows a timed access to ground for capacitor discharge in Astable mode
In English: when the output is low, this allows access to ground so the capacitor can discharge and prepare for the next cycle
Pin 8 – Vcc
Supply Voltage 4.5V – 16V
Only major change in varied supply voltages is that the output drive capacity increases with voltage
Note: a 5V Vcc will cause a 3.3V output signal

4. Internal Organization
The basic organization of a 555 Timer consists of a set of 2 comparators, some transistors, power driver, and a frequency oscillator
The internal comparators compare 2/3 Vcc with the Threshold voltage and 1/3 Vcc with the trigger voltage.
These comparisons are used to determine if the external capacitor should be charged or discharged.
The capacitor is charged or discharged for ½ the period of time.
The power unit boosts the output signal.

5. Input Output Behavior Pin 2 – Trigger Pin 4 – Reset Pin 6 – Threshold
These input pins actually dictate the behavior of the output, the other pins should remain static

6. Designing a Astable Circuit
Frequency = 1.44 / ( (R1 + 2 R2 ) * C )
Duty Cycle = (R1 + R2 / ( R1 + 2 R2 )
Example
40Khz = 1.44 / ( ( 18Ω + 2*9Ω ) * 1nF )
75% = (18Ω + 9Ω ) / ( 18Ω + 2*9Ω )
Lazy People goto:

7. Schematic Diagram

8. Demonstration

9. References http://www.national.com/ds/LM/LM555.pdf (white papers)