1. Flip Flops
Unit-4

2. Flip Flop A basic sequential circuit is a flip-flop
Flip-flop has two stable states of complementary output values

3. SR Flip Flop

4. SR Flip Flop
SR (set-reset) flip-flop based on two nand gates

5. Clocked SR Flip Flop Circuit
Clock controlled flip-flop changes its state
only when the clock C is high

6. Clocked SR Flip Flop Circuit with Reset
Some flip-flops have asynchronous
preset Pr and clear Cl signals.
Output changes once these signals change, however
the input signals must wait for a change in clock
to change the output

7. Edge Triggered Flip Flop
Edge triggered flip-flop changes only
when the clock C changes

8. Positive Edge Triggered Flip Flop
Positive-edge triggered flip-flop changes only
on the rising edge of the clock C

9. Negative Edge Triggered JK Flip Flop

10. Other Flip Flops T J D Q f K Delay Flip-Flop Toggle Flip-Flop
(D-latch)

11. Race Problem Q f D 1 t
loop
Signal can race around during
= 1

12. Master-Slave Flip Flop ImplementationQ J K f
MASTER
SLAVE
PRESET
CLEAR SI RI
Master transmits the signal
to the output during the
high clock phase and
slave is waiting for the
clock to change this
prevents race conditions

13. Shift Registers

14. Shift Registers

15. RIPPLE Counter

16. UP- COUNTER

17. MOD-3 Counter

18. RING Counter

19. JHONSON Counter