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Resist Resolution Enhancement and Line-end Shortening Simulation

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Presentation on theme: "Resist Resolution Enhancement and Line-end Shortening Simulation"— Presentation transcript:

1 Resist Resolution Enhancement and Line-end Shortening Simulation
SFR Workshop May 24, 2001 Mosong Cheng, Andrew Neureuther Berkeley, CA 2001 GOAL: to investigate the impact of electric-field-enhanced post exposure baking on resist profile; validate resist/lens aberration-based line-end shortening model by 9/30/2001. 5/24/2001

2 Motivation Line-End-Shortening becomes worse as device dimensions shrink to sub-100nm regime. Sources for Degradation of Pattern Fidelity: Resist solution to short wavelength lithography Mask error Substrate reflection Recording media, in particular, undesirable acid diffusion/activation of resist Resist parameters vary from fab to fab Lens aberrations vary across field and from tool to tool 5/24/2001

3 ArF Imaging Modeling by Using Resist Simulation and Pattern Matching
Mask Pattern Imaging/Resist Simulator Resist Profile Resist Parameter Tuner Differential SEM Picture Optimizer is standard. The challenge is to build SEM/SIM comparator 5/24/2001

4 SEM/SIM Comparator - Contrast, Bright, Smooth, Edge
Moving window, threshold 5/24/2001

5 Aerial Image Simulation vs. Post Exposure Baking Simulation
–0.2mm 0mm 0.2mm 5/24/2001

6 Simulation Performance vs. Modeling Complexity (170nm)
5/24/2001

7 Predictability of Models (120nm)
Imaging Model < Base PEB Model < Tuned PEB Model 5/24/2001

8 Electric-Field-Enhanced Post Exposure Bake
Electric-Field-Assisted Top Surface Imaging: a potential solution of resist to enable short-wavelength lithography. Generate acid at the resist surface, induce reaction in bulk resist by EFE-PEB. EFE-PEB applied to optical exposure Resist E photoacid 5/24/2001

9 2002 and 2003 Goals Investigate the impacts of the applied electric field polarity, frequency and magnitude on post exposure bake on e-beam and DUV exposure tools by 9/30/2002. Complete the resist/lens aberrations-based line-end shortening model and validate the simulation in 248nm and 193nm lithography by 9/30/2002. Enable 3D EM simulation of substrate topography effects by 9/30/2002. Optimize the electric-field-enhanced post exposure baking process by 9/30/2003. 5/24/2001


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