1. Fundamentals of VLSI and Fabrication Technology1
EE 4121 : VLSI Design and Technology
Instructor
Abu Syed Md. Jannatul Islam
Lecturer, Dept. of EEE, KUET, BD
Department of Electrical and Electronic Engineering
Khulna University of Engineering & Technology
Khulna-9203

2. A Brief History Vacuum tubes Point contact Germanium transistor2
Vacuum tubes
These devices would control the flow of electrons in vacuum.
Boeing B-29 would consist of vacuum tubes. Each additional component would reduce the reliability and increase trouble-shooting time.
Point contact Germanium transistor
1947, John Baden, William Shockley and Watter Brattain of Bell labs discovered this
Bipolar Junction Transistor (BJT)
In 1950, Shockley developed the first Bipolar Junction Transistor (BJT)
First Integrated Circuit
In 1958, Jack Kilby of Texas Instruments
two bipolar transistors connected on a single piece of silicon, thereby initiating the “Silicon Age”

3. Scale of Integration 3
Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining hundreds of thousands of transistors or devices into a single chip.
IC’s----FF’s
2 Transistor
1958
IC’s
More than
1 Billion Transistor
2018
Dual Core+ Core I7 (2015): 1.9billion and 22nm
This scale of growth has resulted from a continuous scaling of transistors and other improvements in the Silicon manufacturing process.

4. Integration & Moore’s Law4
1965: Gordon Moore(Intel cofounder) plotted transistor on each chip
Moore's law: The number of transistors in a dense integrated circuit will be doubled about every two years. 
Integration Levels
SSI: 10 gates
MSI: gates
LSI: 10,000 gates
VLSI: > 10k gates

5. Place for Integration 5
Clean Room: a low level of environmental pollutants 
Company: Apple, IBM, AMD etc.

6. Why Technology Scaling ?6
The demand for battery-operated portable gadgets have increased day by day with tons of applications including hearing aids, cellular phone, laptops etc.
The “basic requirements” of such an application are less area, lower power consumption and cheaper development.
For such portable devices, power dissipation is important because the power provided by the battery is rather limited. Unfortunately, battery technologies cannot be expected to improve the battery storage capacity by more than 30% every five years. This is not sufficient to handle the increasing power needed in portable devices.

7. Scaling and Technology Node7
By making transistors smaller, more circuits can be fabricated on the silicon wafer and therefore, the circuit becomes cheaper. The reduction in channel length enables faster switching operations since less time is needed for the current to flow from drain to source.
In other words, a smaller transistor leads to smaller capacitance. This causes a reduction in transistor delay. As dynamic power is proportional to capacitance, the power consumption also reduces. This reduction of transistor size is called scaling.
Each time a transistor is scaled, we say a new technology node has been introduced. The minimum channel length of transistor is called the technology node. For example, 0.18 micrometer, 0.13 micrometer, 90 nanometer etc.
The scaling improves cost, performance and power consumption with every new generation of technology.

8. Why MOS not BJT in Integration ?8
Early ICs used NMOS technology, because the NMOS process was fairly simple, less expensive and more devices could be packed into a single chip compared to CMOS technology. The first microprocessor was announced by Intel in 1971.
In 1963, F. Wanlass and C. Sah of Fairchild unveiled the first logic gate in which n-channel and p-channel transistors were used in a complementary symmetric circuit configuration. This is what is known as CMOS today. It draws almost zero static power dissipation.
One of the drawbacks of BJT is more static power dissipation. It means that power is drawn even when the circuit is not switching. This limits the maximum numbers of transistors that can be integrated into a single silicon chip.

9. NMOS & CMOS 9
As static power dissipation of NMOS transistor is more compared to CMOS, the power consumption of ICs became a serious issue in the 1980s as thousands of transistors were integrated into a single chip. 
Due to features like low power, reliable performance and high speed, CMOS technology would adopt and replace NMOS and bipolar technology for nearly all digital applications.
NMOS
CMOS

10. Scaling with CMOS 10
CMOS
Scaling and improvement in processing technologies have led to continuous enhancement in circuit speeds
Improvement in packaging densities of chips
Performance-to-cost ratios of microelectronics-based products

11. Overview of Processing Technologies11
Although a number of processing technologies are available, the majority of the production is done with traditional CMOS.
Other processes are limited to areas where CMOS is not very suitable (like high speed RF applications)

12. VLSI Design Cycle 12
The VLSI Design cycle starts with a formal specification of a VLSI chip follows a series of steps, and eventually produces a packaged chip

13. IC Fabrication 13
The fabrication steps are sequenced to form three dimensional regions that act as transistors and interconnects that form the network

14. Chip Fabrication Processes14

15. Chip Fabrication Processes15
„Silicon Wafer Manufacturing„(CZ, FZ, Bridgeman..)
Wafer Processing
Deposition/Epitaxial Growth (MBE, MOCVD…)
Oxidation…
Patterning/Lithography
Removal/Etching
Diffusion and ion implantation…
Annealing/Activation of the implanted dopants. …
Metallization„(Sputtering..)
Testing, Assembly and Packaging

16. Crystal and Wafer Fabrication19

17. Crystal and wafer 20
A polished wafer

18. Wafer Processing 21
In semiconductor device fabrication, the various processing steps fall into four general categories:
Deposition,
Removal,
Patterning, and
Modification of electrical properties.
Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others
Removal is any process that removes material from the wafer; examples include etch processes (either wet or dry) and chemical-mechanical planarization (CMP).

19. Wafer Processing 22
Patterning is the shaping or altering of deposited materials, and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a photoresist; then, a machine called a stepper focuses, aligns, and moves a mask, exposing select portions of the wafer below to short wavelength light; the exposed regions are washed away by a developer solution. After etching or other processing, the remaining photoresist is removed by plasma ashing.
Modification of electrical properties has historically entailed doping transistor  sources and drains (originally by diffusion furnaces and later by ion implantation). These doping processes are followed by furnace annealing or, in advanced devices, by rapid thermal annealing (RTA); annealing serves to activate the implanted dopants. Modification is frequently achieved by oxidation, which can be carried out to create semiconductor-insulator junctions.

20. Syllabus Fabrication and Processing Technology:23
Fabrication and Processing Technology:
Crystal growth, wafer preparation, photolithography, oxidation, diffusion, ion implantation, epitaxi, metallization, etching, NMOS and CMOS fabrication technology.
Testing and packaging:
Overview of silicon semiconductor technology, power dissipation, packaging, silicon on insulator.
Introduction to GaAs technology:
Ultra-fast VLSI circuits and systems.

21. Tests and References Two Class test. One/Two Spot test.24
Two Class test.
One/Two Spot test.
At least Lecture
Copies of chapters will be provided when appropriate
Recommended book:
VLSI Technology by S. M. SZE (Available in Market)
Silicon VLSI Technology by Plummer
Other references: Will be provided in due time.