1. Xiou Ge Motivation PDN Simulation in LIM Real Example Results
Power Distribution Networks Simulation Using Latency Insertion Method
Xiou Ge
Mentor: Xu Chen Advisor: José E. Schutt-Ainé
Motivation
Ensuring power integrity is a challenge in designing future high-performance chips.
Accurately simulating power-supply noise in the on-chip PDN using memory and time efficient approaches is essential.
Applying LIM on simulation has the following advantages:
Requires O(n) memory;
Requires O(n) time per time step;
Independent of the on-chip PDN geometry
Independent of the packaging technologies
LIM Network with interconnect topology
Each branch must contain an inductance
Each node must provide a capacitive path to ground
Lumped Circuit Simulation
Circuit simulated
Simulation Result
Future: extend the program to simulate transmission line model, as well as more complicated network. The ultimate goal is to simulate the PDN network.
PDN Simulation in LIM
Convert on-chip PDN to the equivalent circuit.
Insert latency: add shunt capacitance to ground to nodes, add series inductance to branch to enable the equivalent circuit to be simulated by LIM
Real Example
R, L, C Parameters of Power-Ground Lines in Different layers
Via Resistance, Inductance and Crossover Capacitance
Results
Comparison of the differential voltage LIM method with that from HSPICE.
Time and Memory Requirements
Skills Gained and Future Work
Skills gained:
Programming in Matlab
Numerical Method
Circuit Simulations
Future Work:
Proposed Scheme is conditionally stable
Need to come up with modifications that’s unconditionally stable to improve efficiency
Implement Alternating Direction Explicit Latency Insertion Method
Locally Implicit LIM: apply ideas from block LIM
Try to implement the Latency Insertion method in C
“We would like to give special thanks to Professor
José E. Schutt-Ainé and the Signal Integrity Research Group for their help in this project.
Metal layer
R (Ω/m)
L (H/m)
C (F/m) M1
7.357e-7
1.884e-10 M2
6750
1.3e-6
0.0 M3
3750
1.425e-6 Nn
Via Res(mΩ) Nt
Time taken per time step
Memory
1.9K
1.78fs
168K
0.058s
1.02MB
181K
5.8s
92.7MB
Metal Layer
Via Res(mΩ)
Via Ind (pH)
Crossover Cap.
M1 -M2
34.5
1.47
0.4
M2- M3
13.5
2.6
1.63
References:
[1] Lalgudi, S.N.; Swaminathan, M.; Kretchmer, Y., "On-Chip Power-Grid Simulation Using Latency Insertion Method," Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.55, no.3, pp.914,931, April 2008
[2] Schutt-Aine, J.E., "Latency insertion method (LIM) for the fast transient simulation of large networks," Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on , vol.48, no.1, pp.81,89, Jan 2001