1. The Processor

2. LEGv8 LEGv8 : Simplifed ARM v8 instruction set Comparison to ARM v7
Data Path Width
64 bit
32 bit
Registers
32 (X0, X1, X2, …)
16 (r0, r1, …)
Instruction Names
LDUR
STUR
CBZ
LDR
STR
CMP and BEQ

3. Data Path View
Data Path : Core circuitry to execute instructions

4. Data Path View
Often omits key details
Ex: can’t join two signals:

5. Control View
Control logic is interleaved with data path Data = Black Control = Blue Mux Select 0: top 1: bottom

6. Data Path View
Add : ALU that only adds

7. Goals Explore data path for limited set of instructions LDR, STR
R Type (ADD, etc…)
Branch
Unconditional : B
Conditional : CBZ

8. SUB r4, r5, r6
PC has instruction address

9. SUB r4, r5, r6
Passed to Read address

10. SUB r4, r5, r6
Instruction bits for rn and rm are sent to Read registers 1 & 2 RegWrite = 0

11. SUB r4, r5, r6
r6 comes out of Read data 2, goes through MUX ALUSrc = 0

12. SUB r4, r5, r6
ALU gets r5 from Read data 1, r6 from MUX ALUOp = 0110

13. SUB r4, r5, r6
ALU Result goes to Mux MemToReg = 1

14. SUB r4, r5, r6
MUX goes to Write Data. Rd bits from Instruction to Write register RegWrite = 1

15. SUB r4, r5, r6
Also need to advance PC…

16. SUB r4, r5, r6
Add gets PC Value

17. SUB r4, r5, r6
Mux gets PC + 4 from Add PCSrc = 0

18. SUB r4, r5, r6
PC gets PC + 4 from Mux

19. B loopstart
PC has instruction address

20. B loopstart
Passed to Read address

21. Branch Instruction Format
24 bit immediate
Shifted left 2 bits to make 26 bit value
Sign extended to 32 bits
Signed 26 bit value to be added to PC
+/- 32Mbytes

22. B loopstart Address bits from IM to Sign Extender 32 bits for ARMv7

23. B loopstart
Extended value to shifter

24. B loopstart
Add gets shifted value and PC

25. B loopstart
Mux gets PC + shifted value
PCSrc = 1

26. B loopstart
PC gets PC + shifted value from Mux

27. LDR Trick LDR rd, [rn, #immediate] : Calculate rn + immediate
Get value at that memory address into rd

28. LDR r4, [r5, #0]
PC has instruction address

29. LDR r4, [r5, #0]
Passed to Read address

30. LDR r4, [r5, #0] Read register 1 gets bits for rn from Instruction
RegWrite = 0

31. LDR r4, [r5, #0]
Immediate bits of instruction( 0) get sign extended

32. LDR r4, [r5, #0]
Mux gets extended immediate ALUSrc = 1

33. LDR r4, [r5, #0]
ALU gets rr from Read data 1. Gets 0 from Mux ALUOp = 0000

34. LDR r4, [r5, #0]
Data Mem gets r from ALU
MemRead =1 MemWrite = 0

35. LDR r4, [r5, #0]
Mux gets Read data
MemToReg = 0

36. LDR r4, [r5, #0] Write register gets bits for Rd (r4) from instruction
Write data gets data from Mux
ReadWrite = 1