1. by Brian Wheatman and Elaine Gan
Cache Coherence
by Brian Wheatman and Elaine Gan

2. How Far We Got… Our sixcache deadlocks on mc_multiply2
Our stq and lhusm fail on only 2 tests
mc_incrementers and mc_spin_lock
Deadlocking and livelocking

3. Difficulties Coding and Debugging
Parent Protocol Processor
Getting things mutually exclusive without imposing arbitrary order
Deadlocking in Ex5
MessageRouter could not fire due to implicit guard
splitting into two rules

4. Difficulties Coding and Debugging
Trouble with Ex. 8 (mc_spin_lock & mc_mulitply2)
spent hours for what ended up being a typo
Where we are now
SixCache - debugging why there is livelocking

5. Difficulties Understanding the Protocol
Fairness in dealing with child requests in MessageRouter
Didn’t surface until mc_incrementors in Ex 8
When to downgrade or invalidate

6. What Improvements? For the Class
a better understanding of what bluespec does with the code
Perhaps some examples from actual processors

7. What Improvements? For the Final Project
More even split between Part 1 and Part 2
More individual testing
Exercise 5 – whole mem hierarchy
Give out the assignment earlier
or have some stages be done for earlier labs