1. Equalization/Compensation of Transmission Media
Channel
(copper or fiber)
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 1

2. Optical Receiver Block Diagram
O  E
TIA LA EQ
CDR
DMUX
Optical signal can have varying amplitude; gain of O-E converter is fixed. Thus limiting amplifier is required to deliver constant amplitude to input of EQ/CDR.
EQ often required to compensate for distortion from the channel. (Will discuss shortly.)
≈ -18 dBm
≈ 10 µA
≈ 10 mV p-p
≈ 400 mV p-p
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 2

3. Copper Cable Model Where: L is the cable length
4-foot cable
15-foot cable
Copper Cable
Draw impulse response on the board.
Emphasize that energy needs to be added mainly up to 5GHz to restore the signal.
Where: L is the cable length
a is a cable-dependent characteristic
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 2

4. Effect of Copper on Broadband Data
waveform
eye diagram
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 3

5. Adaptive Analog Equalizer for Copper
Will demonstrate a case study
Implemented in Jazz Semiconductor SiGe BiCMOS process:
120 GHz fT npn
0.35 µm CMOS
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 4

6. Equalizer Block Diagram
5GHz peaked amplifier will restore high frequencies near baud rate that are lost in copper cable. (Assuming monotonically decreasing cable characteristic)
With more equalization required, 5 GHz is more emphasized.
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 5

7. Analog Equalizer Concept (1)
Simple linear circuit (normalized to 1Hz): 1 V2 V3 V1
+0.5
-0.5 1 1 1 1 C1 1s
simple channel model
bandpass filter
combined flat response
+ peaked response
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 6

8. Analog Equalizer Concept (2)1 C1 V1 V2 V3
-0.5
+0.5 1s V1 V2
Note V1 has widely varying pulse width (down to 0), but not the case for V2. Weighted sum will give some dc component as well as increase pulse width.
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 7

9. Analog Equalizer Concept (3)
Rise time = voltage swing/slew rate
Equalized output pulses: V3
Rise time nearly constant over different channels!
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 8

10. Feedforward Path Vout EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 9

11. Equalizer Frequency Response
Vcontrol
This figure shows the simulated ac response for 3 different values of Vcontrol.
The upper curve coresponds to a lower Vcontrol. We have noted that the equalization setting primarily affects the low frequency gain
f (Hz)
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 10

12. ISI & Transition Time VFFE t (ns) 2.4 2.5 2.6 2.7 2.8 -0.3 0.3
teq = 75ps
PW = 86ps
teq = 60ps
PW = 100ps
2.4
2.5
2.6
2.7
2.8
t (ns)
-0.3
0.3
VFFE
teq = 45ps
PW = 108ps
This confirms the theoretical study shown earlier.
Simulations indicate that ISI correlates strongly with FFE transition time teq.
Optimum teq is observed to be 60 ps.
Nonlinearities affect pulse shape, but not location of zero crossings.
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 11

13. Slicer Restores full logic levels Exhibits controlled transition time
This slicer is implemented by two cascaded CML buffers. The first buffer ehibits fast transition time and corrects the signal amplitude. This limiting is critical because the equalizer output exhibits large over shoots even when the ISI is minimized. The second buffer produces an output with a fixed transition time that optimize the output ISI. This optimal transition time is achieved when the obseved output exhibits the lowest ISI.
Possible questions:
how did you find the optimal rise fall time? How can you tell for difference cable?
Restores full logic levels
Exhibits controlled
transition time
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 12

14. Feedback Path
The feedback path is shown here where you can see the two detectors are designed to give an output pulse whose engergy is proportional to the input transition time. The pulses are then applied to the differential inputs of an integrator. The integrator output resonds to the difference of the transition time between the detector inputs. When the adaptive loop reaches steady state, v control will be set such that the equalizer output will exhibit the same transition time as the slicer output.
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 13

15. Transition Time Detector
DC characteristic:
ISS
CSS VS V+ V-
Transient Characteristic: t
(a)
(b)
Rectification & filtering done in a single stage.
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 14

16. Integrator
The integraor , designed using standard CMOS techniques, gives an output control voltage Vcontrol that is proportional to the energy in the pulsesat the output of the detectors. This voltage is the fed back to the equalizer. A common mode feedback is designed to improve the stability. The transfer function of the integrator can be approximated as:
where……….
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 15

17. Detector + Integrator FFE transition Time tFFE Vcontrol (mV) 90ps 75ps
From
FFE
tFFE
From
Slicer
tslicer= 60ps
Vcontrol (mV)
90ps 60
slope
detector
slope
detector 40
75ps 20
60ps
-20
45ps
-40
-60
15ps 10 20 30 40 50 _ +
t (ns)
Vcontrol
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 16

18. System Analysis Kd H(s) Keq Kd Keq = 1.5 ps/mV Kd = 2.5 mV/ps
tslicer
detector
Vcontrol
integrator
feedforward
equalizer
teq + Kd
H(s)
Keq _
detector Kd
This analyzes the overall dynamics of the adaptation loop. It depends on the characteristic of each component.
Keq = 1.5 ps/mV
Kd = 2.5 mV/ps
int = 75ns
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 17

19. Measurement Setup Die under test 231 PRBS signal applied to cable
EQ inputs
Die under test
EQ outputs
231 PRBS signal
applied to cable
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 18

20. Measured Eye Diagrams EQ output EQ input 4.0 ps rms jitter
4-foot
RU256 cable
(-5 dB 5 GHz)
4.0 ps rms jitter
15-foot
RU256 cable
(-15 dB 5 GHz)
3.9 ps rms jitter
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 19

21. Summary of Measured Performance
Supply voltage
3.3 V
Power Dissipation
350 mW
(155 mW not including output driver)
Die Size
0.81mm X 0.87mm
Output Swing
490 mV single-ended p-p
Random Jitter
4.0 ps rms (4-foot cable)
3.9 ps rms (15-foot cable)
This table is the summary of measured performance. (read the table)
Presented at ISSCC Feb. 2004
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 20

22. Equalization vs. Compensation
Equalization is accomplished by inverting the transfer function of the channel.
Compensation is accomplished only by canceling the ISI at each unit interval.
Electronic Dispersion Compensation (EDC) refers to the electronics that accomplishes compensation of copper or optical transmission media.
EDC is becoming especially critical as bit rates increase on legacy equipment (e.g., backplane, optical connectors, optical fiber).
The previous example showed an analog equalizer. This is used for only well-behaved channel characteristics.
We’ll now consider methods for Electronic Dispersion Compensation (EDC), which works on a bigger set of channel characteristics.
(Will use term equalization even in compensation systems.)
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 21

23. Pre-Cursor/Post-Cursor ISI
Input pulse (no ISI):
For this exercise we’ll consider a single-ended pulse (baseline at 0).
cursor
pre-cursor ISI
post-cursor ISI T
Output pulse:
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 22

24. Feedforward Equalization (FFE)
Idea: To cancel ISI, subtract a weighted & delayed version of the pulse:
output pulse delayed by T:
d-1
To cancel other pre- or post-cursor ISI, we can have more delays and subtractions. In general, we need the same number of weighted sums as there are sampling points to make zero. d0
output pulse:
Result with 0 pre-cursor ISI:
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 23

25. Feedforward Equalization (2)
Time domain: a1 _ + 
This is consistent with intuition that such an equalizer would be HPF.
Note low-frequency gain < 1.
Frequency domain: 
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 24

26. Feedforward Equalization (3)
N-tap FFE structure: T T T
Post-cursor distortion can be cancelled by setting cursor in the middle instead of far left. a0 a1 a2 an 
FFE can cancel both pre- and post-cursor distortion.
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 25

27. Feedforward Equalization (4)
3-tap summing circuit:
ISS V0 V1 V2 R
Vout + _
negative coefficient
For “well-behaved” channels, coefficients usually alternate in sign. If not, we would need a more elaborate structure.
Delay elements are set by CML circuit with unity gain and set delay. (Will show example later.)
Coefficients set by gm of each differential pair.
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 26

28. Feedforward Equalization (5)
Fractional spacing: 
1-tap T-spaced FFE frequency response
Equalization at higher frequencies can be accomplished with fractional spacing -- that is, delays that are less than 1UI. Result is sharper rise & fall times.
Eye diagram correspond to LPF channel + FFE.
5-tap T-spaced FFE eye diagram 
1-tap T/2-spaced FFE frequency response
5-tap T/2-spaced FFE eye diagram
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 27

29. Adaptation (1) Assume original sequence Din(k) is known.
Define error signal e(k) as: ^ ^
where Dout(k) is an appropriately delayed version of Din(k).
Steepest Descent Algorithm: a1 a2
optimum
setting
Will talk about how error is generated shortly.
Dout_hat corresponds to an appropriate delay that comes from the channel and assignment of which tap is the cursor.
step size
Algorithm moves coefficients in direction of decreasing mean-square error.
Step size µ should be made sufficiently small to guarantee convergence.
Requires knowledge of properties of mean-square error; usually not available.
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 28

30. Adaptation (2) Least mean-square (LMS) algorithm: FFE output signal: ^
In LMS we instead use the immediate value of e rather than its average.
For sufficiently small step size, on average, the correction should move in the correct direction of decreasing e^2. In the realization of LMS, each tap requires a multiplication and summation (or integration).
Analog version of LMS:
both signals are available on chip.
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 29

31. Adaptation (3) Types of adaptation: 1. Training Sequence
A training sequence with known properties is sent through the channel + equalizer. The equalizer output is compared to the original sequence and an error signal is generated.
Blind adaptation is preferable, especially considering slowly varying changes in channel characteristic.
This was already shown in the analog equalizer example earlier.
2. Blind Adapation
Adaptation is continually performed while system is running. Only limited properties of the signal are known. An error signal must somehow be generated without having the original sequence.
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 30

32. Adaptation (4)  Generation of error signal: ^ FFE _ +
Slicer restores logic levels and opens eye vertically.
Bit sequences at slicer input & input are identical.
Slicer has no effect on placement of zero crossing.
Slicer can be realized using CML buffers with sufficient gain and speed.
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 31

33. Decision Feedback Equalization (DFE) a0 a2 an
FFE structure:
Noise applied to FFE input will be retained (perhaps filtered) at the output.
Resembles the FFE but flipped horizontally and vertically.  T b1 b2 bm + -
DFE structure:
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 32

34. Decision Feedback Equalization (2) T b1 b2 bm + -
Slicer is embedded in the structure; Dout is a digital signal.
Delay elements are digital -- commonly realized by DFFs.
Use of slicer suppresses input noise.
Cancels post-cursor distortion only.
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 33

35. Decision Feedback Equalization (3)
post-cursor distortion  T b1 b2 bm + -
1-tap example:
2/3
1/3 1
consistent with
(desired) 1
Tap weights provide a “look-up table,” canceling post-cursor distortion based on last m bits of output sequence.
DFE can sometimes “latch up” with wrong tap weights during adaptation.
2/3
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 34

36. FFE + DFE T a1  a0 a2 an b1 b2 bm + -
Combined FFE and DFE can be used to cancel both pre- and post-cursor distortion with low noise.
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 35

37. Front-End Circuits for DSP-Based Receivers
Vin
PGA
ADC
AGC VC VA
Dout [1:n]
from channel
ADC requires strict control over its input amplitude VA.
Automatic Gain Control
Programmable Gain Amplifier (PGA):
where
“Linear in dB” gain characteristic gives settling time independent of input amplitude.
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 36

38. PGA Design 1. Differential Pair: VC + _ Vin+ Vin- Iout- Iout+ ISS
For biasing in weak inversion:
2. Source Degeneration:
2RS
Vin+
Vin-
Iout-
Iout+
3. Op-Amp with Feedback:
Vin + _
Vout RS Rf
RS varied with constant dB per step.
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 37

39. PGA Example (1) Realization of RS: 2 dB steps
C.-C. Hsu, J.-T. Wu, “A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier,” JSSC, Oct. 2003, pp
Realization of RS:
2 dB steps
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 38

40. gain of single diff. pair
PGA Example (2)
J. Cao, et al., “A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s links over backplane and multimode fiber,” ISSC 2009, pp
gain of single diff. pair
where N = number of diff. pairs turned on
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine 39

41. Track & Hold Circuit
The T/H circuit is comprised of two switch-capacitor stages and an amplifier which provides gain and isolation.
Dummy switches are used to cancel channel charge injection and achieve better linearity. 40

42. T/H differential output for fin = 1.5 GHz and fs=10 GS/sec
Simulation Results
T/H differential output for fin = 1.5 GHz and fs=10 GS/sec 41

43. High-speed Comparator
High-Level Clocking:
Improves isolation between the input and output, reducing kickback from output.
Cascoding of the clock switches reduces the Miller effect of the input transistors.
Reduced headroom 42

44. Comparator/Latch Results (1)43

45. Metastable Behavior (1)
Comp./Latch output
T/H output
Metastable event
What is the probability of this error occurring? 44

46. Metastable Behavior (2)Ct v1 + − v2 t 45

47. Metastable Behavior (3)
Vin (analog)
Vout (digital) 1 2 3 01 10 11 00 +e -e
-Vdec
+Vdec 2e
2Vdec
VLSB
Vdec = minimum detectable logic level
e = minimum input at t = 0 so that output level is ≥ Vdec at t = T/2
Error probability:
Including comparator gain: 46

48. Metastable Behavior (4)
Recall:
For error-free operation after half-clock period: t
Error probability: 47

49. Reducing Metastability Errors
Additional high-speed latches following the comparator/latch stage reduces probability of metastable events at the output.
Latch output 48