1. Overview of SHARC processor ADSP-2106X Compute Operations*
07/16/96
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Overview of SHARC processor ADSP-2106X Compute Operations
M. R. Smith, Electrical and Computer Engineering, University of Calgary, Alberta, Canada
ucalgary.ca *

2. To be tackled today Reference sources Register file and operations
ALU operations
MAC operations (Multiply and accumulate)
SHIFTER operations
Common errors
Example exercises
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ENCM Review of SHARC Processor
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3. Reference Sources
ADSP-2106x SHARC User’s Manual 2nd edition, Analog Devices -- provided to everybody
Subset of ADSP-211XX processor operations
ENCM515 SHARC Reference card
ENCM515 Course, Reference and Laboratory Notes
Check web-pages for links to VisualDSP++, Compiler, Assembler, Linker and other tools
Also see ECE-ADI-Project (link from Dr. Smith Home Page)
SHARC Navigator Tutorial Tool
See January 2004 web pages for link – shows basic assembly language operations using simple animation
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ENCM Review of SHARC Processor
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4. Picture Source
SHARC Navigator Tutorial Tool T. Talik Alukaidey Dept. of EEE Uninversity of Hertfordshire, Hatfield, U.K.
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ENCM Review of SHARC Processor
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5. ADSP-2106x Core Architecture*
ADSP-2106x Core Architecture
07/16/96
DAG 2
8 x 4 x 24
DAG 1
8 x 4 x 32
CACHE
MEMORY
32 x 48
PROGRAM
SEQUENCER
PMD BUS
DMD BUS 24
PMA BUS
PMD
DMD
PMA 32
DMA BUS
DMA 48 40
JTAG TEST &
EMULATION
FLAGS
FLOATING & FIXED-POINT
MULTIPLIER,
FIXED-POINT
ACCUMULATOR
32-BIT
BARREL
SHIFTER
FLOATING-POINT
& FIXED-POINT
ALU
REGISTER
FILE
16 x 40
BUS CONNECT
TIMER *

6. Register File and COMPUTE Units
Key issues
5 data paths FROM COMPUTE units
5 data paths TO COMPUTE units
Highly parallel operations UNDER THE RIGHT CONDITIONS
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7. Register File – BIT STORAGE
Key issues
40 bits wide
Top 32 bits used for integer
Top 32 bits used for float
40 bits for precision float
32 registers available 16 at a time
A Register is always 40 bits
can be processed as a float
can be processed as an integer
Must convert integer<-> float
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SHADOW

8. Instruction format Instructions are 48 bits wide
23 bits – COMPUTE field – are available for computer operations – See appendix B-1
Single-function format
11-8 destination 7-4, 3-0 – source register
19-12 opcode associated with computation unit (bits 21-20) (ALU, MAC or SHIFTER)
Bit 22 always a 0 for single function format
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9. Sample ALU Instructions
SEE REF-CARD
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10. Register File Common mistake – handling R0 and F0 registers
Contains “bit patterns”, not floating point or integer values
Patterns might represent floats or integers
Floating point characteristics of an instruction reside in the ALU behaviour and not in the registers themselves
Example
R0 = 0x ; ASSEMBLY INSTRUCTION means Move “bit pattern” 0x into R0
F0 = 2.0; IS AN ASSEMBLER DIRECTIVE means Move “bit pattern” for 2.0 (0x ) into R0 -- disassembles as R0 = 0x ;
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11. ALU instructions -- Common errors
Key issues -- what IS NOT there rather than what IS there -- REMEMBER -- Superscaler RISC DSP CPU
Rx = Ry + CONSTANT; NOT THERE
Rtemp = CONSTANT; This twin instruction
Rx = Ry + Rtemp; MUST be used COMMON TIME WASTER IN LABS WHEN NOT CHECKED.
COMMON MARK LOSER ON EXAMS and QUIZZes
NOTE: -- Rx = constant is not an ALU operation but an Immediate Move Universal Register instruction bringing in a value from PROGRAM memory as part of the op-code -- MOVEQ equivalent
Ureg = <data32>
This issue is important when trying to issue parallel operations in a given instruction
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12. ALU instructions -- Common errors
Key issues -- what IS DIFFERENT rather than what IS the SAME –
REMEMBER -- processor designed for DSP
Rx = Ry * Rz; Does not behave as on 68K
On 68K
MULTS D0, D1 is a 2’s complement multiply (signed)
MULTU D0, D1 is an unsigned multiply
On 21XXX
Rx = Ry * Rz; is a signed signed fractional multiply (SSF)
Rx = Ry * Rz (SSI); is a 2’s complement multiply (signed signed integer)
The other forms of multiply commonly needed in integer DSP algorithms are available (UUI, UUF, SSFR, etc.)
2’s complement numbers require shifts after multiplication to keep them valid – SSF numbers don’t.
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13. Volatile registers on ADSP-21XXX
Volatile registers – work as on 68K
Must follow “C/C++” compiler conventions
VisualDSP++ V3.0 with SP1
No need to save when in subroutine
4 register banks (because of special parallel operations)
1 volatile register in each bank
R0, R4, R8, R12
And also R1
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14. Practice Examples
Convert from “C” into assembly code – use volatile registers
long int value = 6;
long int number = 7;
long int temp = 8;
value = value + 1;
number = number + 2;
temp = value + number;
float value = 6;
float number = 7;
long int temp = 8;
value = value + 1;
number = number + 2;
temp = value + number;
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ENCM Review of SHARC Processor
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15. Practice Examples
Convert from “C” into assembly code – use volatile registers
long int value = 6;
long int number = 7;
long int temp = 8;
value = value + 1;
number = number + 2;
temp = value + number;
4/12/2019
ENCM Review of SHARC Processor
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16. Practice Examples
Convert from “C” into assembly code – use volatile registers
float value = 6;
float number = 7;
long int temp = 8;
value = value + 1;
number = number + 2;
temp = value + number;
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17. MAC instructions -- mainly INTEGER Multiply and Accumulate
SSI and SSF
SEE REF-CARD
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18. Practice Examples
Convert from “C” into assembly code – use volatile registers
long int value = 6;
long int number = 7;
long int temp = 8;
value = number * temp;
float value = 6;
float number = 7;
long int temp = 8;
value = number * temp;
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ENCM Review of SHARC Processor
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19. Avoiding common design errors
Convert from “C” into assembly code – use volatile registers
long int value = 6;
long int number = 7;
long int temp = 8;
value = value + 1;
number = number + 2;
temp = value + number;
float value = 6.0;
float number = 7.0;
long int temp = 8;
value = value (float) 1;
number = number (float) 2;
temp =
(int) (value + number);
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ENCM Review of SHARC Processor
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20. Avoiding common design errors
Convert from “C” into assembly code – use volatile registers
long int value = 6;
long int number = 7;
long int temp = 8;
value = number * temp;
float value = 6.0;
float number = 7.0;
long int temp = 8;
value =
number * (float) temp;
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21. Shifter Instructions -- mainly integer
SEE REF-CARD
FPACK is a cast and means (32bit -> 16bit) Fx
UNPACK is a cast and means (16bit -> 32bit) Rx BUT WITH A LOT OF HIDDEN STUFF TOO!
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22. Examples long int value = 6; long int number;
number = value >> 2;
#define value_R0 R0
#define number_R4 R4
number_R4
= ASHIFT value_R0 BY –2;
POSITIVE VALUE – LEFT SHIFT
NEGATIVE VALUE – RIGHT SHIFT
long int value = 6;
float number;
number = value >> 2;
#define value_R0 R0
#define temp_R1 R1
#define number_F4 F4
temp_R1
= ASHIFT value_R0 BY –2;
number_R4 = FLOAT temp_R1; Or
number_F4 = FLOAT value_R0 BY –2;
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23. 21061 ALU instructions
Under the RIGHT conditions can do multiple operations in a single instruction
Certain Ops using certain registers -- see reference material
1 MAC, 1 ALU (SOMETIMES 2), AND 1 DM ACCESS, 1 PM ACCESS Certain combinations can also be CONDITIONAL We are going to write code in a format that will allow us to parallel instructions -- an expectation for the course
Depends on what you do and who you do it to (special registers combos)
only a certain number of bits available in opcode (40 bits) so that not all reasonable combinations possible
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24. Multi-function examples
Fm = Fx + Fy, Fn = Fx – Fy;
Note that uses 4 different registers and not 6
The source registers used around the + and – must be the same.
Restriction as 4 registers MUST be described using 16 instruction bits
Fm = Fa * Fb, Fn = Fc + Fd;
Fa MUST be one of F0, F1, F2, F3
Fb MUST be one of F4, F5, F6, F7
Fc MUST be one of F8, F9, F10, F11
Fd MUST be one of F12, F13, F14, F15
Restriction as 6 registers MUST be described using only 16 instruction bits
4/12/2019
ENCM Review of SHARC Processor
Copyright

25. Tackled today Reference sources Register file and operations
ALU operations
MAC operations (Multiply and accumulate)
SHIFTER operations
Common errors
Example exercises
4/12/2019
ENCM Review of SHARC Processor
Copyright