1. FF - TB May 10th, 20051 L1 L0 FANOUT LOGIC ALICE general Trigger layout FEE LTU CTP L0 BUSY FEE L1 TTC vi VME BUS L2a, L2r L0 TTC ex CH A CH B L2a, L2r L0 L1, L2a, L2r (LVDS) BUSY (OPT FIBER) TRIG INPUTS (LVDS) BUSY L0 (LVDS) BUSY BUSY FANIN LOGIC MEB (ECL) OPT SLITTER L1 (ECL) (OPT FIBER) TRIG I/P FANIN LOGIC (LVDS)

2. FF - TB May 10th, 20052 Results of LVDS fan-in/fan-out survey (Orlandos slide at 11/4/05 TB)

3. FF - TB May 10th, 20053 Conclusions: L0 FANOUT and BUSY + TRIG I/P FANIN units Proposed technical solution VME 6U units plugged in LTU partition crates (probably need of 2 more crates) Fanout: 1 LVDS IN - 12 LVDS OUT (limited by front panel mechanics) Optional clocked delays to compensate cable lengths (25ns steps, 10-20 steps) Important: minimum input/output latency required (50ns or better) Jumpered cable shield GND connection (shorted or through a resistor) Fanin: 12 LVDS IN - 1 LVDS OUT (limited by front panel mechanics) Optional remote controlled channel masking Optional clocked delays to compensate cable lengths (25ns steps, 10-20 steps) Jumpered cable shield GND connection (shorted or through a resistor) Compatible signal standard at IN and OUT: same LVDS Tx and Rx as in LTU same connectors as in LTU Number of units (from Orlandos survey) 10 Fanins and 15 Fanouts Detectors asked to agree on technical solution and confirm quantities Looking for collaborator(s) that are prepared to make the design Time scale for availability: March 2006 (proto end of 2005)

4. FF - TB May 10th, 20054 LVDS trigger cables Needed for: L0 fanout + Busy fanin + Trigger inputs to CTP Cable lengths of 50 - 70m Compensation at receiver side to correct for: risk of loosing pulses variation of pulse duty cycle Based on passive equalizer to plug in front of the unit receiver connector THR End of differential shielded pair Output of differential Rx (÷10 probe) THR PSpice 100m cable and source models Measured 100m cable

5. FF - TB May 10th, 20055 LVDS transmission Differential current source transmitter LVDS Tx Normal typ output current ( 3.5mA) LVDM Tx Double typ output current ( 7mA) Single 3.3V supply 1.2V 700mV @ Z o =100Ω 50mV I out ZoZo Tx Rx tr, tf < 1ns Tx = TI 65LVDM31 4 ch, 7mA, LVDS driver t pd = 3ns Max Rx = TI 65LVDS32B 4 ch, 50mV hysteresis, LVDS receiver -2V / +4.4V Common Mode T pd = 6ns Max Differential voltage discriminator receiver Differential signal hysteresis = 50mV or 100mV Output high if input unconnected or shorted Single 3.3V supply Texas Instruments evaluation board +4.4V -2.0V

6. FF - TB May 10th, 20056 Cable equalization principle 1)Maximization of the media bandwidth according to Max acceptable signal attenuation 2)Conservation of the cable termination impedance PSpice 100m cable equalization Measured 100m cable attenuation Cable Equalizer Equalized cable -16dB Atten. Cable -16dB = Max acceptable signal attenuation with: Worst case (min) current source at Tx ( 5.4mA for LVDM Tx) Worst case (max) hysteresis cycle at Rx, times safe margin of 2 ( 100mV for LVDS Rx) High impedance cable (120Ω) to maximize signal voltage at Rx (this is also better cable) Equalized cable

7. FF - TB May 10th, 20057 Test results 120Ω 262Ω (261Ω) 160pF (150pF) 148Ω (150Ω) 1.15μH (1μH) 100m Draka Li-2Y(St)H 3x2x0.088mm 2 3x shielded twisted pairs Z 0 = 120Ω ±10% Without cable equalizer With cable equalizer Rx output (÷10 probe) End cable positive signal Rx Passive cable equalizer

8. FF - TB May 10th, 20058 Conclusions: trigger cables Done simulations and tests of: 100m Draka Li-2Y(St)H 3x2x0.088mm2 (3x shielded twisted pairs – 4.7ns/m) Passive cable equalization showed safe working conditions up to 100m: equalizer to be implemented in compact solution Draka could build single shielded pair with same characteristics for Alice: under verification through C. Dechelette Estimated total cable length for whole ALICE: ~13Km from Orlandos L0 and Busy table and 50m average per cable ~2.5Km for the CTP inputs cables (based on 50 Inputs and 50m average) ~5Km reserve for future use TOTAL ~ 20Km