1. COMP541 Combinational Logic - 3
Montek Singh
Jan 28, 2019

2. Today’s Topics Synthesis: Schematic drawing conventions
from truth table to logic implementation
Schematic drawing conventions
Non-Boolean values
“Don’t Cares”, or X values
“Floating values”, or Z values

3. Mechanically Go From Truth Table to Function

4. From Truth Table to Logic Equation
Consider a truth table
Standard sum-of-products implementation
OR of all product terms that are 1
For each row where output is 1
write the minterm
called “ON-set minterm”
OR all of these minterms

5. Standard Forms Not necessarily simplest F Definitions:
But it is a systematic way to go from truth table to function
Definitions:
“Literal”: a single variable, complemented or not  Ā
“Product terms”: AND of literals  ĀBZ
“Sum terms”: OR of product terms  X + Ā
This is logical product and sum, not arithmetic

6. Definition: Minterm
Product term in which all variables appear once (complemented or not)
each minterm is 1 in exactly one row, 0 elsewhere

7. Number of Minterms For n variables, there will be 2n minterms
Like binary numbers from 0 to 2n-1
Often numbered same way (often in decimal)

8. Definition: Maxterm
Sum term in which all variables appear once (complemented or not)
each maxterm is 0 in exactly one row, 1 elsewhere

9. Minterm related to Maxterm
Minterm and maxterm with same subscripts are complements
Example

10. Implementation: Sum of Minterms
OR all of the minterms of truth table row with a 1
“ON-set minterms”
F = m0 + m2 + m5 + m7
Example:

11. More General: Sum of Products
Simplifying sum-of-minterms can yield a sum of products
difference is that each term need not be a minterm
i.e., terms do not need to have all variables
Ex:
Implementation is still AND-OR
but products may contain fewer literals
simplifies to:

12. Two-Level Implementation
Sum of products has 2 levels of gates
ANDs followed by an OR
equivalently: NANDs followed by a NAND

13. More Levels of Gates? What’s best? Hard to answer
More gate delays (more on this later)
But maybe we only have 2-input gates
So multi-input ANDs and ORs have to be decomposed

14. Complement of a Function
Definition: 1s & 0s swapped in truth table
Mechanical way to derive algebraic form
Take the dual
Recall: Interchange AND and OR, and 1s & 0s
Complement each literal

15. Complement of F Not surprisingly, just sum of the other minterms
sum of “OFF-set minterms”
Example:
F = m0 + m2 + m5 + m7
F’ = m1 + m3 + m4 + m6
simplifies to:

16. Product of Maxterms
Recall that maxterm is true except for its own case
So M1 is only false for 001

17. Product of Maxterms
Can express F as AND of all rows that should evaluate to 0
i.e., product of OFF-set Maxterms!
why?
a row in which F=0 (OFF-set)…
… has a Maxterm that is 0
which makes the product 0 or

18. Complement of F Can express complement of F similarly: or
product of ON-set Maxterms of F!
why?
a row in which F=1 (ON-set)…
… has a Maxterm that is 0
which makes F’ zero or

19. More General: Product of Sums
Simplifying product-of-Maxterms can yield a product of sums
difference is that each term need not be a Maxterm
i.e., terms do not need to have all variables
Ex:
Implementation is still OR-AND
but each sum may contain fewer literals
simplifies to:
HOW??  homework problem
(hint: distributive property)

20. From Equations to Gates
Simply parse the Boolean equation and replace each operator with a gate
AND, OR, NOT gates
parentheses indicate hierarchy
Example:

21. Gate-level realization: Sum-of-Products
AND-OR can be simply turned into NAND-NAND
DeMorgan’s law indicates equivalence
common because NANDs are basic gates in CMOS logic

22. Gate-level realization: Product-of-Sums
OR-AND can be simply turned into NOR-NOR
DeMorgan’s law indicates equivalence
common because NORs are basic gates in CMOS logic

23. Recap Working (so far) with AND, OR, and NOT Algebraic identities
Algebraic simplification
Minterms and maxterms
Can now synthesize gate-level implementation from truth table

24. Drawing Style Indicate inputs and outputs using arrows
or: inputs at left/top, outputs at right/bottom
If possible, gates should flow from left to right
or: top to bottom
Straight wires best
or: keep bends at a minimum (preferably 90 deg)
Connections:
wires always connect at a “T” junction
a dot at a wire crossing indicates connection
wire crossing without a dot means no connection

25. Circuit Schematic Rules (cont.)
Wire connections
A dot where wires cross indicates a connection
Wires crossing without a dot make no connection
Wires always connect at a T junction

26. Multiple Output Circuits: Example
Output asserted
corresponding to
most significant
TRUE input
Example: Priority Encoder Hardware

27. Example: Priority Encoder Hardware (contd.)
Y3 has 8 minterms, Y2 has 4 minterms, Y1 has 2 minterms and Y0 has 1
without simplification: 15 AND gates + 3 OR gates
with simplification, a much smaller circuit (method discussed later)

28. Values that are not 0’s and 1’s
Don’t Cares (X)
Floating values (Z)

29. X values X is neither 1 nor 0 Unknown Don’t Care Illegal
typically used to represent “unknown” or “illegal” values
Unknown
e.g., an uninitialized value in a simulator
in hardware most flipflops will wake up to a 1 or a 0 value
but could be different each time it wakes up
Don’t Care
an output specified as X means “don’t care”
i.e., left unspecified: whatever comes out is okay
Illegal
e.g., contention at output
two gates fighting

30. Actually: Several Meanings of X
When used to specify an input value
Means: “Don’t Care”: this particular input variable’s value does not matter when determining the output
Example: Output F is 1 when the inputs A, B, C are 1X1
Means F = AC // B is a Don’t Care
Unknown/uninitialized signal
If a simulator cannot determine the value of a signal, it will display it as X
Other values that depend on this signal may also become X
Contention (illegal input value)
Sometimes a simulator will use X to denote the value of a node that is being pulled both to 0 and to 1
Example: Outputs of two gates are shorted; or a gate has p-transistor and n-transistor network simultaneously on!

31. Don’t Cares (X) More compact representation!
Example: Priority Encoder Hardware

32. Z values Also neither 1 nor 0 Could be undesirable:
but actually “floating”
i.e., the output is neither connected to 0 (ground) nor to 1 (power supply)
Could be undesirable:
actual voltage is highly susceptible to noise
e.g., neighboring wires/gates could easily influence value
Could be by design:
useful in buses, memories, multiplexers, etc.
usually one gate drives a wire to a 1 or 0
all others “float” their outputs
example: tristate buffers/inverters
cover in next lecture
tristate buffer

33. Next Detour Back to combinational logic overview of transistors
common building blocks