1. Xilinx Kintex7 SRAM-based FPGA
9th APRIL 2018
SpacE FPGA Users Workshop - SEFUW
Analysis and Mitigation of Single Event Upsets in Configuration Memory of
Xilinx Kintex7 SRAM-based FPGA
Sarah Azimi, Luca Sterpone, Boyang Du
David Merodio Codinachs
Politecnico di Torino- CAD Group
Dipartimento di Automatica e Informatica
Torino- Italy

2. Boyang DU - SEFUW2018- Noordwijk- The Netherlands
Motivations
SRAM-based FPGA
High performance
High device density (more configurable resources)
High flexibility (partial reconfiguration etc.)
SRAM cell holding configuration data is highly susceptible against SEU induced by charged particle
Space Application
Performance
Mission critical: Reliability requirement
Harsh Environment: charged particles
When SRAM-based FPGA is to be deployed in space applications, it has to be verified regarding SEEs induced by radiation effects.
Boyang DU - SEFUW2018- Noordwijk- The Netherlands

3. Boyang DU - SEFUW2018- Noordwijk- The Netherlands
Collaboration with ESA
SEE analysis and mitigation techniques for programmable devices: Flash-based and SRAM-based
SEU in configuration memory FPGA
Xilinx Virtex5
Proton test in PSI
Neutron test in ISIS and Los Alamos
New opportunity with facility in CERN
Ultra High Energy Heavy Ion Beam
Xilinx Kintex 7 device
Paper accepted in NSREC2018
SET in Flash-based FPGA
Heavy Ion test in UCL
A set of analysis and mitigation tools available
VERI-Place, SETA, SET-PAR etc.
Boyang DU - SEFUW2018- Noordwijk- The Netherlands

4. Boyang DU - SEFUW2018- Noordwijk- The Netherlands
Outline
Introduction
Background
Radiation Experiment
Experiment Results
Conclusion and Future Works
Boyang DU - SEFUW2018- Noordwijk- The Netherlands

5. SRAM-based FPGA Introduction Main concern: SEU in configuration memory1 1 1
Configuration Memory
Circuit design mapped on FPGA
Boyang DU - SEFUW2018- Noordwijk- The Netherlands

6. Boyang DU - SEFUW2018- Noordwijk- The Netherlands
Background
Traditional Solutions
Redundancy based
Xilinx TMR Tool
Scrubbing
“Periodically” rewrite / fix configuration memory
Partial reconfiguration based
Error detection
Mitigate permanent fault
Boyang DU - SEFUW2018- Noordwijk- The Netherlands

7. VERI-Place Tool Proposed Method: VERI-Place Tool
Error rate prediction w.r.t. SEU in configuration memory
Improve design reliability against SEU in configuration memory though Place and Route constraints
No hardware overhead
Easy to be integrated into standard design flow
Boyang DU - SEFUW2018- Noordwijk- The Netherlands

8. VERI-Place Tool Proposed Method: VERI-Place Tool Error Rate Prediction
FPGA Architecture Database
VERI-Place
Error Rate Prediction
Custom Constraints
Post-Layout
Netlist
Gate-Level Netlist
HDL/High Level Design
Synthesis
Bitstream
Place & Route
BitGen
Timing Database
Design Constraints (Timing, Power etc.)
Design Constraints (Timing, Power etc.)
Boyang DU - SEFUW2018- Noordwijk- The Netherlands

9. Boyang DU - SEFUW2018- Noordwijk- The Netherlands
Radiation Experiment
Ultra High Energy Heavy Ion Test beam in CERN
First time open for third party radiation tests
Xenon heavy ion beam
energy level set to 40GeV/n
effective LET ~3.7 MeV∙cm2/mg using FLUKA considering volume around 1µm3
Boyang DU - SEFUW2018- Noordwijk- The Netherlands

10. Boyang DU - SEFUW2018- Noordwijk- The Netherlands
Experiment Setup
Hardware
Kintex7 XC7K325T SRAM-Based FPGA
28nm technology
ARM-based SoC
Software
Bubble sort using UART as output
Boyang DU - SEFUW2018- Noordwijk- The Netherlands

11. Boyang DU - SEFUW2018- Noordwijk- The Netherlands
Experiment Setup
Hardware
Kintex7 XC7K325T SRAM-Based FPGA
28nm technology
ARM-based SoC
Version
LUT [#]
LUT [%]
FF [#]
FF [%]
BRAM [#]
BRAM [%]
Plain_SoC
3,907
1.91%
1,189
0.29% 4
0.89%
Plain_x50
195,074
95.72%
59,460
14.59%
200
44.94%
XTMR_SoC
18,760
9.20%
9,057
2.22% 12
2.70%
XTMR_x10
187,557
92.03%
90,572
22.22%
120
26.97%
Boyang DU - SEFUW2018- Noordwijk- The Netherlands

12. Test Setup (Hardware) Experiment Setup Kintex7 Zybo
Zynq Processing System
UART OUTPUT
UART
RST
Program; Readback
Program; Data Transfer
USB
USB PC
Boyang DU - SEFUW2018- Noordwijk- The Netherlands

13. Boyang DU - SEFUW2018- Noordwijk- The Netherlands
Experiment Setup
Test Flow
Boyang DU - SEFUW2018- Noordwijk- The Netherlands

14. Two Versions of the design
Radiation Test Campaign
Two Versions of the design
Plain
XTMR
[XTMR-VP]: Based on XTMR version with VERI-Place mitigation tool applied.
(Originally) 12 Hours Slot
Some hours occupied by tests on Flash-based FPGA, due to low LET, no SET observed
Real effective test hours 4~5 hours
Plain: 136 runs; XTMR: 16 runs
Boyang DU - SEFUW2018- Noordwijk- The Netherlands

15. Boyang DU - SEFUW2018- Noordwijk- The Netherlands
Experiment Results
Error Rate
Application Error: when a mismatch at the UART output comparing to golden data
Boyang DU - SEFUW2018- Noordwijk- The Netherlands

16. Boyang DU - SEFUW2018- Noordwijk- The Netherlands
Experiment Results
Error Rate Cross-Section
Boyang DU - SEFUW2018- Noordwijk- The Netherlands

17. Boyang DU - SEFUW2018- Noordwijk- The Netherlands
Experiment Results
Patterns
Possibility of SEMU
Single point/bit of failure -> Single area of failure
Boyang DU - SEFUW2018- Noordwijk- The Netherlands

18. New radiation test results
Conclusions & Future Work
New radiation test results
Ultra High Energy Heavy Ion Test beam in CERN
Xilinx Kintex-7 SRAM-based FPGA
ARM-based So(P)C
VERI-Place error rate prediction
VERI-Place mitigated version being planned
Comparison with Virtex5 test results
Boyang DU - SEFUW2018- Noordwijk- The Netherlands

19. Thank you very much for your attention! Q&A
Boyang DU - SEFUW2018- Noordwijk- The Netherlands