1. NS Training Hardware

2. SPI-Boot

3. SPI-Boot Strapping option on pin reset_done
Hardware configures SPI interface
Hardware configures memory interface
Hardware configures external SDRAM
Configuration information is stored in a header starting at address zero in the SPI-EEPROM
ARM9 Wake-Up upon completion
New feature for the NET+ARM family

4. SPI-Boot Limitations Supports SPI-EEPROM devices from 2Kb up to 32Mb
Supports only clock mode (0,0) SPI-EEPROM devices
Supported only on SPI port A

5. SPI-EEPROM Boot System

6. SPI-EEPROM Read Access