Download presentation
Presentation is loading. Please wait.
1
Electrical and Computer Engineering Department
CMOS Nanoelectronics Durga Misra Electrical and Computer Engineering Department NJIT Newark, NJ 07102 April 13, 2019
2
Outline Nanoelectronics Historical Perspective Power Requirements
High-K Gate Dielectrics Dielectric Characterization Future’s Trends Summary April 13, 2019
3
April 13, 2019
4
ELECTRONICS Electronics
There were many inventions in the 20th century: Airplane, Nuclear Power generation, Computer, Space aircraft, etc However, everything has to be controlled by electronics Electronics Most important invention in the 20th century What is Electronics: To use electrons, Electronic Circuits or IC (Integrated Circuits) Without IC, Mobile phone cannot be made, for example. April 13, 2019
5
ELECTRONICS Bipolar using Ge 1947: 1st transistor
This is the 1st Transistor: Not Field Effect Transistor, But Bipolar Transistor (another mechanism) 1947: 1st transistor J. Bardeen W. Bratten, Bipolar using Ge W. Shockley April 13, 2019
6
Winner of the 2000 Nobel Prize
ELECTRONICS 1958: 1st Integrated Circuit Jack S. Kilby Winner of the 2000 Nobel Prize Connect 2 bipolar transistors in the Same substrate by bonding wire. April 13, 2019
7
A New Form of Transistor -- 1962
Metal-Oxide Semiconductor Field-Effect Transistor Radio Corporation of America (RCA) Sarnoff Laboratories Gate Gate Drain Drain Source Source W W p+ n+ p+ n+ L L n p - - type body (bulk) type body (bulk) April 13, 2019
8
ELECTRONICS April 13, 2019
9
Al Gate Si Source Drain Si Cross-section Top View Al SiO2 Si
1960: First MOSFET by D. Kahng and M. Atalla Top View Cross-section Al Al Gate Si SiO2 Source Si Exceptionally good interface! Very small number of interface charges Drain Si April 13, 2019
10
Complimentary MOS (CMOS)
Silicon Nano-CMOS April 13, 2019
11
Intel Pentium 4 mProcessor -- 2003 55 million transistors
April 13, 2019
12
System-on-Chip (SoC) Design Revolution
Advantages: On-chip interconnects are many times faster than off-chip wires Get a compact system with the same functionality Reduces pin overhead Saves much power Reduces noise in the mixed-signal circuits Liabilities Bed-of-nails (decomposition) system testing is not possible Most of the cores are surrounded by many other cores Results in very poor controllability and observability Need electronic test hardware to access these blocks during testing Until now Physical Components ASIC design System-on-Board Integration From now Logical Components Design IP Blocks System-on-Chip Integration April 13, 2019
13
Moore’s Law 1965: Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale Transistor counts have doubled every 26 months Integration Levels SSI: 10 gates MSI: gates LSI: 10,000 gates VLSI: > 10k gates April 13, 2019
14
CMOS Scaling: Moor’s Law Continues CPU with Multimedia Capability
Number of transistors on a chip in thousands 1 1b 100,000 10,000 1,000 100 10 '70 '75 '80 '85 '90 '95 '00 '05 '15 '10 processors ‘25 ‘20 ‘30 100b 10b Moore’s law prediction 100-billion transistors 1-billion transistors Pentium III Xeon Pentium II Pentium III Pentium Pro Pentium 80386 80486 80286 4004 8086 8080 April 13, 2019
15
April 13, 2019
16
64k DRAM 3 inch wafer 1979 64k DRAM 4 inch wafer 1980 1k SRAM
1974 April 13, 2019
17
After 45 Years from the 1st single MOSFET
32 Gb and 16Gb NAND, SAMSUNG April 13, 2019
18
Nanoelectronics — Nano-CMOS
Silicon Nano-CMOS: Challenges Process Technologies and Devices 100 nm : Brick Wall. 50 nm : Iron Wall ? 10 nm : Steel Wall ? 6 nm : Galaxy Wall ? Architectures, Integration, and Applications Multimedia CPU with 100 billion transistors Tera-Bit DRAM Nano-SOC April 13, 2019
19
CMOS Power/Speed Issues
April 13, 2019
20
High-K has Arrived SiO2 layers <1.6 nm have high leakage current due to direct tunnelling. Not insulating Maintain Capacitance/area for S-D current Replace SiO2 with thicker layer of new oxide with higher K Equivalent oxide thickness ‘EOT’ April 13, 2019
21
High-K: Polysilicon vs. Metal Gates
IEEE Spectrum October 2007 April 13, 2019
22
Characterization of High-K Films
E. A. Cartier, SEMATECH 2nd Int. Wkshp. on Adv. Gate Stacks Tech., 83 (2005) April 13, 2019
23
Reliability Issues in High-K Gate Stack Charge Trapping
Negative Bias Temperature Instability (NBTI) Time Zero Dielectric Breakdown (TZDB) Time Dependent Dielectric Breakdown (TDDB) IEEE TDMR 06 IEEE IRPS 07 April 13, 2019
24
High Mobility Channels – Ge
Most important feature of Si technology is SiO2 If no SiO2, could use other semiconductor – Ge More symmetric and higher carrier mobilities (low-field) more efficient source carrier injection due to lower effective mass Presently use strained Si Combine High-K (HfO2) with Ge substrate Ge Si April 13, 2019
25
NBTI, Interface States and SILC
Nitrogen Degrades Interface and Bulk Properties But seems to suppress GeO2 formation Rahim & Misra, IEEE IRPS 2008 April 13, 2019
26
What is Nanotechnology?
Switching devices of nanometer ( typically 10nm) dimensions define nanotechnology. Emerging Nanotechnology Solutions Emerging Nanotechnology Drivers Quantum Dots SETs CNFETs Logic (Our Focus) Molecular RTD Nano CMOS CNT arrays Molecular orientations as Bits DNA strands as Bits Memory DNA self assembly Molecules in Solution Self assembled CNT using DNA Fabrication April 13, 2019
27
Summary Moore’s Law continues to hold but major technical obstacles at present are: Lithography Technology and Design complexity of 1 billion transistor single chip High-K Gate Dielectrics helps reduce power VLSI Designers are increasingly asked to do analog chip layout and sensors on silicon - Computer Aided Design Tools are constantly changing - VLSI models are increasingly required April 13, 2019
28
Thank You Questions? April 13, 2019
Similar presentations
![EE314 Basic EE II Silicon Technology [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]](/16/5137281/big_thumb.jpg "EE314 Basic EE II Silicon Technology [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]>")
