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Datapath and Control Exceptions
5.6
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Goal Build an architecture to support the following instructions
Arithmetic: add, sub, addi,slt Memory references: lw, sw Branches: jump, beq
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Process Design basic framework that is needed by all instructions
Build a computer for each individually Add MUXes to choose between different operations Add control signals to control the MUXes
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MIPS trends Get an ____________ from memory using the ______________ (___) Read ____ or _____ registers each instruction _____ register: _____ registers:
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MIPS trends All instructions use ______ after reading regs Some instructions also access _______ Write result to ________
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Framework Use ALU Get instruction from memory Read from register file
Access memory Write register file
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What *exactly* is memory?
Interface: reads: input output writes: Variation Multi-ported May read or write multiple items at the same time Must add inputs / outputs
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Instruction Fetch Where are instructions stored? ________
How do we know where to fetch and instruction? ___________ What happens to the PC each instruction? ____________ By how much does the PC change? _____ What determines this amount? _________ Is the PC one of the 32 regs? Why or why not?
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Get Instruction
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“Add” instruction Where does the instruction tell what registers to read? Where does the instruction tell what register to write?
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“Add” Instruction Operation rs rt rd shamt funct # meaning add 3 5 2
32 # $2 <- $3 + $5 Read Addr Out Data Instruction Memory PC 4 op/fun rs rt rd imm src src1data src src2data Register File destreg destdata Instruction
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“Addi” Instruction Operation rs rt imm # meaning addi $5,$3,6 3 5 6
# $5 <- $3 + 6 Read Addr Out Data Instruction Memory PC 4 op/fun rs rt rd imm src src1data src src2data Register File destreg destdata Instruction
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Sign Extension How do we go from 16-bit number to 32-bit number?
How about 4-bit to 8-bit. 0111 = 7 = ________ 1110 = -2 = ________ So, how do we do it?
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Reading/Write Registers
When does register get written? What would happen if we allowed write to occur at any time?
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Putting them together Instruction Memory op/fun rs rt rd imm
Read Addr Out Data Instruction Memory PC 4 op/fun rs rt rd imm src src1data src src2data Register File destreg destdata Instruction
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Putting them together Control Unit 4 Register File PC op/fun rs rt rd
ALUOp ALUSrc 4 RegDest src src1data src src2data Register File destreg destdata PC op/fun rs rt rd imm Read Addr Out Data Instruction Memory Inst M U X M U X 16 Sign Ext 32
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Machine Speed What determines the clock rate of a machine? _____________________ Making something bigger makes it:
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Load Word (lw) Operation rs rt imm # meaning lw $5,8($3) 3 5 8
Read Addr Out Data Instruction Memory PC 4 op/fun rs rt rd imm src src1data src src2data Register File destreg destdata Instruction
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Addr Out Data Data Memory In Data
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Store Word (sw) Operation rs rt imm # meaning sw $5,8($3) 3 5 8
Read Addr Out Data Instruction Memory PC 4 op/fun rs rt rd imm src src1data src src2data Register File destreg destdata Instruction 16 Sign Ext 32
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Address calculation identical to load word
Out Data Data Memory In Data
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Putting them together Instruction Memory op/fun rs rt rd imm
Read Addr Out Data Instruction Memory PC 4 op/fun rs rt rd imm src src1data src src2data Register File destreg destdata Instruction 16 Sign Ext 32
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Addr Out Data Data Memory In Data
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Putting them together Data Memory Control Unit 4 Register File PC
MemWr MemRd ALUOp 4 RegWrite Addr Out Data Data Memory In Data src src1data src src2data Register File destreg destdata PC op/fun rs rt rd imm Read Addr Out Data Instruction Memory Inst 16 Sign Ext 32
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Ld/St Questions Are the data and instruction memory the same thing? How do they differ?
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Ld/St Questions What is the advantage to split memory?
What is the advantage to unified memory?
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Beq What ALU operation are we going to perform?
We add a ______ bit as an output to the ALU. To perform a jump, we need to change the ________
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beq Operation rs rt imm # meaning Beq $3,$5,lp 3 5 6
# if ($3 == $5) goto lp Read Addr Out Data Instruction Memory PC 4 op/fun rs rt rd imm src src1data src src2data Register File destreg destdata Instruction
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Beq The immediate field is the number of _____________ to advance.
The address is expressed in ___________. Each instruction is _____ bytes We need to multiply the # instructions by ______ or shift left by _____
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Jump Instruction The absolute address is stored in the target – do not add to current address Absolute address is only ______ bits PC is ______ 32 We get the top bits by Sign extending target? Concatenating target?
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j (jump) Operation Target address # meaning J loop 0x0174837
# goto loop Read Addr Out Data Instruction Memory PC 4 op/fun rs rt rd imm src src1data src src2data Register File destreg destdata Instruction
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The Whole Shebang Data Memory << 2 << 2 4 Register File PC
Addr Out Data Data Memory In Data src src1data src src2data Register File destreg destdata PC op/fun rs rt rd imm Read Addr Out Data Instruction Memory Inst 16 Sign Ext 32
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Exceptions 5.6
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Unexpected Events Internal External
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Definitions Anything unexpected happens PowerPC External event occurs
Internal event occurs Change in control flow Exception Interrupt PowerPC Intel MIPS
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Exception-Handling Stop Transfer control to OS Tell OS what happened
Begin executing where we left off
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1. Detect Exception Add control lines to detect errors
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Step 2: Store PC into EPC Data Memory << 2 << 2 4
Addr Out Data Data Memory In Data src src1data src src2data Register File destreg destdata PC op/fun rs rt rd imm Read Addr Out Data Instruction Memory Inst 16 Sign Ext 32
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Step 3: Tell OS the problem
Store error code in the _________ Use vectored interrupts Use error code to determine _________
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Cause Register Set a flag in the cause register
How does the OS find out if an overflow occurred if the bit corresponding to an overflow is bit 5?
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Vectored Interrupts The address of trap handler is determined by cause
Exception type Exception vector address (in hex) Undefined Instruction C hex Arithmetic Overflow C hex
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Cause Register – Go to OS
Handler PC << 2 -4 Cause << 2 4 EPC Addr Out Data Data Memory In Data src src1data src src2data Register File destreg destdata PC op/fun rs rt rd imm Read Addr Out Data Instruction Memory Inst 16 Sign Ext 32
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Vectored Interrupt – Go to OS
Cause Vector Table << 2 << 2 -4 4 EPC Addr Out Data Data Memory In Data src src1data src src2data Register File destreg destdata PC op/fun rs rt rd imm Read Addr Out Data Instruction Memory Inst 16 Sign Ext 32
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