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Logic Design LAB 7 授課老師:伍紹勳 課程助教:邱麟凱、江長庭.

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Presentation on theme: "Logic Design LAB 7 授課老師:伍紹勳 課程助教:邱麟凱、江長庭."— Presentation transcript:

1 Logic Design LAB 7 授課老師:伍紹勳 課程助教:邱麟凱、江長庭

2 Multiplexer Outline Requirement 8 to 1 multiplexer
LS to 1 multiplexer Lab

3 Requirement IC:74151 x 1、7404 x 1、7408 x 2、LED x 1、Switch x 1、220Ω電阻 x 8

4 8 to 1 multiplexer

5 LS to 1 multiplexer

6 Lab Implement How to convert Y to F ?

7 Lab Inspect equations and we can find that Draw K-map to reduce F!
F has sum of 9 products Y has sum of 8 products Draw K-map to reduce F! If we reduce F to less or equal than 8 SOP, then we can use Y to represent F

8 Lab Example Reduce And we can get

9 Lab Reduce again And we can get

10 Lab Please use other reduce method to do this lab LS 74151


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