1. Process Technology Development
Sang-Uk Ahn
Process Technology Development

2. Major Process Modules Isolation (Shallow Trench)
Twin Well (Retrograde)
Transistor Formation
Multi-level Metallization

3. Process Feature

4. Process Feature (cont.)

5. Design Rule

6. Device Performance

7. Cross Sectional View - Stacked Via
PWELL
NWELL
SUBSTRATE
Pwell Contact
MET 1
PMD OX
N-ch transistor
P-ch transistor
ISO OX
IMD 4
MET 4
IMD 3
MET 3
IMD 2
MET 2
IMD 1
MET 5
PO OX
PO NIT
VIA 3
VIA 4
VIA 2
VIA 1
CONT
Nwell Contact
N-well P+
Poly
GATE
DRAIN
SOURCE
aa XXXXC07 Process

8. Transistor Structure
PETEOS
HSQ
Metal 1

9. Metal 1 CD : 0.32 um @ Structure : Ti/TiN/Al-Cu/TiN
IMD Profile
0.64 um
PETEOS
HSQ
Metal 1
Metal 1 CD : 0.32 um @ Structure : Ti/TiN/Al-Cu/TiN

10. Construction Analysis
( SRAM Cell : Stacked Via )
IMD3
Metal 3 stack
SOG
Via2
IMD2
Metal 2 stack
SOG
Via1
IMD1
SOG
Metal 1 stack
W-C/T
PMD
Tr.

11. SEM Cross Sectional View- Stacked Via

12. Correct the specific features
OPC Implementation
Purpose
To compensate proximity effect of wafer processing
Rule Based OPC
Correct the specific features
according to the rules
Model Based OPC
Impose an inverse distortion
to cancel the proximity effect

13. OPC Example
Rule Based OPC
Model Based OPC
Layout w/