Advanced Computer Architecture Systolic Organization

Advanced Computer Architecture Systolic Organization
A.R. Hurson 128 EECH Building, Missouri S&T

Advanced Computer Architecture
To effectively utilize a given technology, the constraints of that technology must be well understood. System designers must consider the limitations of the technology to design a system where those limitations do not impact the overall performance significantly.

It is generally accepted that many computational tasks are by their very nature sequential, and for others the degree of parallelism varies. To maintain sufficient application flexibility and computational efficiency, a massively parallel computational architecture must offer reconfigurability, scalability, and programmability.

reconfigurable — to exploit application dependent parallelisms, high level language programmable — to provide task control and flexibility, scalable — to easily extend the architecture to many applications, capable of supporting SIMD organizations for vector operations and MIMD for non homogeneous parallelism requirements.

Systolic operation and organization is a design philosophy that is aimed to satisfy the architectural constraints imposed by the advances in silicon technology. It offers simplicity, regularity, modularity, and localized communications.

Systolic arrays are typically characterized as having intensive local communications and computations yet, with decentralized parallelism in a compact package. Systolic arrays capitalize on processes which can be performed in a regular, modular, rhythmic, synchronous, and concurrent manner that require intensive repetitive computations.

Systolic arrays originally were proposed for fixed or special purpose instances, however, this concept has been extended to more general purpose SIMD and MIMD architectures.

What is a Systolic Arrays? There is no uniquely accepted definition for systolic arrays or systolic cells. The term systolic originated in the medical community where it is used to describe the human circulatory system. Systolic processes, like the circulatory system, perform the operations in a rhythmic, incremental, cellular, and repetitive manner much like the heart circulating blood through the arteries, veins, and capillaries.

What is a Systolic Arrays? The systolic computational rate is restricted by the array's I/O operations, much the same way that the heart controls blood flow to the cells. The term array originates from the observation that systolic arrays have balanced uniform architectures which typically look like grids: Each line indicates a communication path. Each intersection represents a cell or a systolic element.

What is a Systolic Arrays? Systolic arrays are more than processor arrays which execute systolic algorithms. A systolic cell takes on one of the following forms: A special purpose cell with hardwired functions, A vector-computer-like cell with instruction decoding and a processing element or, A systolic processor complete with a control unit and a processing unit.

General Systolic Organization

In 1978, the first systolic arrays were introduced as a feasible design for special purpose devices which meet the VLSI constraints. These special purpose devices were able to perform four types of matrix operations at high processing speeds: matrix-vector multiplication, matrix-matrix multiplication, LU-decomposition of a matrix, Solution of triangular linear systems.

Although, systolic architectures originally, were motivated for high performance special purpose computational systems that meet the constraints of VLSI, however, it is possible to design systolic systems which have high throughputs and yet are not constrained to a single VLSI chip.

Systolic Characteristics Systolic architectures are composed of a few basic building blocks — faster design time. Basic building blocks are replicated in a one, two, or possibly higher dimensional space. The systolic cells use simple and regular communication paths to their nearest neighbors — To eliminate broadcasting of data throughout the system. Regular interconnections also lead to higher densities and shorter communication paths.

Systolic Characteristics The systolic cells are synchronized by a single global clock. The input data streams are fed to the systolic array only at its boundaries. Different data streams can flow in different directions at different speeds through the array.

Systolic Characteristics Systolic architectures have some characteristics similar to pipelined or array processor configurations.

Systolic Characteristics Systolic architectures differ from pipelined systems because; Most of the stages are identical, Input data is not consumed, Input data streams can flow in different directions, Modules may be organized in a two-dimensional (or higher) configuration.

Systolic Characteristics Systolic architectures differ from array of processors because; Processors in systolic organizations are synchronized by a single global clock, but are locally controlled — different systolic cells can perform different operations at the same time.

Systolic Characteristics Systolic architecture have several advantages over conventional systems: Systolic architectures make the design of special purpose systems easier — cost-effective special purpose systems. Systolic architectures are also well suited for the constraints of many technologies — especially VLSI.

Systolic Characteristics Systolic architectures allow higher throughputs — concurrent operations of a large number of the processing cells. Ability to increase the execution speed of compute-bound applications without increasing the I/O requirements — reusability of the input data.

Systolic Issues Algorithms and Mapping: Designers must be intimately familiar with the algorithms that they are implementing on systolic arrays. The heuristic design of systolic arrays from an algorithm is slow, error prone, requires simulation for verification, and often results in a non optimum solution. Automatic array synthesis is a research area of interest. However, most array designs are based on heuristics.

Systolic Issues Integration into Existing Systems: Generally, systolic processors are integrated into an existing host as a backend processor.

Systolic Issues Integration into Existing Systems: System integration is often nontrivial because of the array’s high I/O requirements. Often, an additional memory subsystem is added between the existing host and the systolic array to support data access and data multiplexing and de-multiplexing since the existing I/O channel of the host rarely satisfies the bandwidth required by the systolic array.

Systolic Issues Cell Granularity: Low level or high level cell granularity will directly affect the array’s throughput, flexibility, and the set of algorithms which may be efficiently executed.

Systolic Issues Cell Granularity: The basic operation performed in each cycle by each cell can range from logical or bit wise operations to word level multiplication and addition to a complete program. Granularity is subject to technology capabilities and limitations as well as design goals. Packaging will also introduce input/output pin restrictions.

Systolic Issues Extensibility: Since systolic arrays are built around the cellular building blocks, the cell design should be sufficiently flexible to allow it to be used in a wide variety of topologies implemented in a wide variety of substrate technologies.

Systolic Issues Clock Synchronization: Clock lines of different lengths within integrated chips, as well as external to the chips, can introduce skews. Clock skew risk is greater when data flow within the systolic array is bi-directional. Wave-front arrays reduce the clock skew problem by introducing more complicated asynchronous inter cellular communications.

Systolic Issues Reliability: As integrated circuits grow larger and larger, inherent fault tolerant abilities must be added if the same degree of reliability is to be maintained. Also diagnostics should be built in at design time so proper operation can more easily be verified.

Summary Systolic organization Definition Characteristics Issues Systolic vs. Pipelining Systolic vs. array of processor

Systolic Design — Character Matching A straightforward approach to search for a pattern within a string of characters (string) is simple but time- consuming. The following algorithm shows the sequence of operations. The algorithm compares the characters in the pattern against the characters in the text from left to right. This simple algorithm has a time complexity of O(m*n) where m and n are the lengths of the pattern and text.

Systolic Design — Character Matching Search for a Pattern T-index  0; While T-index < (n-m+1) DO Save  T-index; P-index  0; While P-index < m and Textsave = PatternP-index DO Save  Save + 1; P-index  P-index + 1; END If P-index = m then return; T-index  T-index +1;

Systolic Design — Character Matching Concept of the finite state automaton can be used to perform pattern matching operation in a time complexity of O(n). Knuth proposed an algorithm with the time complexity of O(m+n).

Systolic Design — Character Matching The proposed model is used for character matching (pattern Matching) operation. The model is composed of two kind of cells: Comparator cells, and Accumulator cells.

Systolic Design — Character Matching The comparator cells receive text and patterns from opposite directions and generate the Comparison results. The accumulator cells transmit information regarding delimiters and "don't care" signals. In addition, it accumulates the partial match results.

Systolic Design — Character Matching

Systolic Design — Character Matching Algorithm in C cells: Pout  Pin Sout  Sin dout  (Pin = Sin)

Systolic Design — Character Matching Algorithm in A cells: lout  lin Xout  Xin IF lin THEN rout  t; t  True ELSE rout  rin; t  t AND (Xin OR din)

Systolic Design — Character Matching Detect pattern ISSI in text MISSISSIPPI in a systolic organization composed of seven cells.

Systolic Design — Character Matching Initial configuration IPPISSISSIM TEXT ISSI PATTERN

Systolic Design — Character Matching M I M I S M I S

S Systolic Design — Character Matching M I S M I S I S

Re-circulation I S Systolic Design — Character Matching S I S I 11 S I

S I Systolic Design — Character Matching I S I S 15 I S

S P Systolic Design — Character Matching I S P 18 I S P I P

Systolic Design — Character Matching I P I P

Systolic Design — Character Matching General Characteristics Hardware utilization is low, since during each clock pulse only half of the cells are active. Patterns have to be cycled through the array continuously to meet all the text characters. Possible detection of more hits in the input text.

Systolic Design — Join Operation Within the scope of relational databases, join is one of the most time consuming operations.

Assume we have two product-compatible relations (sets) A and B. Each relation is composed of several tuples (records). Further, let  , , , ..., then the -Join of relation A on attribute X with relation B on attribute Y is a relation consist of tuples t(<a,b>) from Cartesian product of A and B such that tx  ty is true. A  B =  a,b  a,b A  B, and tX  tY is true

Systolic Design — Join Operation Assume we have the following two relations: P S

A S.City=P.City B Systolic Design — Join Operation

Systolic Design — Join Operation In relational database system, join operation is used as a measure to evaluate the performance of the system. This is due to the Complexity of the join, and application of join in de-normalizing the relations.

Systolic Design — Join Operation Let us look at a systolic model for join operation: A collection of basic cells replicated in a two dimensional space. System is highly parallel and satisfies the constraints imposed by the VLSI technology.

Systolic Design — Join Operation A Systolic Cell a’s and b’s are the attributes and t is a control signal that reflects the comparison between a and b.

Systolic Design — Join Operation A Systolic Cell Tout  tin  (ain  bin) aout  ain bout  bin

41 14 13 • • • Attributes of A relation in Systolic Design — Join Operation Elements of the Bit Matrix Attributes of B relation in

b11 a12 • b12 • • • Systolic Design — Join Operation

b11 a12 b12 a21 • b21 • • • Systolic Design — Join Operation

b11 a22 • a12 b12 b22 a21 b21 • • • Systolic Design — Join Operation

Systolic Design — Join Operation b11 • a22 a12 b12 b22 a21 b21 b31 a11 a31 a23 a13 a14 b23 b13 b14

Systolic Design — Join Operation b11 a32 • a22 a12 b12 b22 a21 b21 b31 • a11 a31 b32 a13 a14 b13 b14 b23 b24 a23 a24

Systolic Design — Join Operation

Advanced Computer Architecture Systolic Organization

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