1. Local Video System: Overview
EECS150 Fall Lab Lecture #7
Ke Xu
4/18/2019
EECS150 Lab Lecture #8

2. Welcome to Checkpoint 1 First real design checkpoint Video in SDRAM
No datasheets!
Video in SDRAM
Motivation
Storage
FIFO Controllers
SDRAM Arbiter
4/18/2019
EECS150 Lab Lecture #8

3. The Big Idea(1)
4/18/2019
EECS150 Lab Lecture #8

4. The Big Idea(2) Combining checkpoint 1 (SDRAM) + two video modules
We’ll give you the video decoder + video encoder
Video Decoder writes a frame into SDRAM
Video Encoder reads the frame from SDRAM
Arbiter sits between SDRAM Controller and Decoder/Encoder to make sure the SDRAM Controller sees only one request at a time
4/18/2019
EECS150 Lab Lecture #8

5. Video Encoder
Previous semesters had to implement this as a checkpoint.
This semester, the Video Encoder module will be black-boxed.
Saves the class from having an excessive number of checkpoints.
Will be replaced by the last checkpoint, which is video compression (DCT + Huffman).
4/18/2019
EECS150 Lab Lecture #8

6. Short Video Summary ITU-R BT.601 ITU-R BT.656
Luma/Chroma Y CR Y CB Pixel Pairs
Vertical/Horizontal Active/Blanking
4/18/2019
EECS150 Lab Lecture #8

7. Video References Past Lab Lecture on video encoder posted online.
Sample design document (Chen’s) already posted on the website.
Check documentation (ADV7194 Video Encoder, ADV7185 Video Decoder) on website.
Past checkpoint pdf spec also posted online.
4/18/2019
EECS150 Lab Lecture #8

8. Checkpoint 2 Part I: Encode/Decode FIFO Controllers Part II: Arbiter
Address Counters determine read/write addresses
FSM determines when to request read/write
Part II: Arbiter
Need to handle simultaneous requests.
Handles writes from decode processor
Handles reads from encode processor
Ensures that one request is given to SDRAM Controller at a time
4/18/2019
EECS150 Lab Lecture #8

9. FIFO Controllers (1) Decoder FIFO Controller
Store active video data from decoder into FIFO
Write to SDRAM when FIFO has enough data
Assert a write request when FIFO has at least 8 words
Ensures that FIFO does not underflow
Controls the write address counter
Similar to encoder FIFO controller
4/18/2019
EECS150 Lab Lecture #8

10. Dual Clocked FIFO
The FIFO on the decoder side uses two independent clocks: one for reading, one for writing.
The camera runs on its own 27MHz clock.
You can use ModelSim to figure out how to interpret each of the control signals.
4/18/2019
EECS150 Lab Lecture #8

11. FIFO Controllers (2) Encoder FIFO Controller
Reads active video data from SDRAM
Reads from SDRAM when FIFO has enough space
Assert a read request when FIFO is less than ¾ full
Must ensure that FIFO never overflows
Controls the read address counter
Sends data from FIFO to VideoEncoder
4/18/2019
EECS150 Lab Lecture #8

12. More on FIFOs Why a FIFO? Data Rate Matching Buffering
SDRAM handles data at 32 bits per cycle
Encoder handles data at 32 bits per 4 cycles
Buffering
Encoder needs a continuous stream of data
SDRAM might be busy
The FIFO “Predicts” what data the video encoder will want and supplies it upon request
4/18/2019
EECS150 Lab Lecture #8

13. Announcements Checkpoint 1
Checkpoint 1 due next week in your respective lab sections.
Demonstrate working implementation of your checkpoint.
Knowledge of SDRAM Controller timing is essential for checkpoint 2
Please make sure to finish your checkpoints on time.
Once you finish one checkpoint, your attention will then immediately focus on the next checkpoint.
Lateness means you will only fall further behind.
4/18/2019
EECS150 Lab Lecture #8

14. SDRAM Arbiter (1)
Essentially, you’re replacing Checkpoint0bb with your own useful implementation.
Controls interface with SDRAM Controller
Sets priority between Decoder and Encoder
SDRAM Controller thinks there is only 1 port
SDRAM Arbiter allows multiple access ports
Funnels control signals selectively to each port
4/18/2019
EECS150 Lab Lecture #8

15. SDRAM Arbiter (2) You will need to add more states to this 4/18/2019
EECS150 Lab Lecture #8

16. Arbiter Handshaking Protocol
Once the SDRAM Controller has finished initializing, the arbiter will start polling the decoder and encoder for requests (simultaneously).
If both modules are ready, the arbiter should give priority to the encoder.
If neither module is ready, the arbiter should poll again.
If either module is ready, the arbiter must appropriately assert read/write requests to the SDRAM controller, and control signals to the FIFO controllers
YOU MUST REVIEW THE TIMING FOR HANDLING REQUESTS IN YOUR SDRAM CONTROLLER.
THE CONTROL SIGNALS MUST BE TIMED PERFECTLY OR YOUR PROJECT WILL NOT WORK
4/18/2019
EECS150 Lab Lecture #8

17. How is the video data stored?
4/18/2019
EECS150 Lab Lecture #8

18. Modifications Needed for CP0
Recall from Checkpoint 0:
RAM Address = {Row, Bank, Column}
In this checkpoint:
RowAddress = {4’h0, PixelRow, Field}
BankAddress = 2'h0
ColumnAddress = {BurstColumn, 3'h0}
You will modify your address counter to accommodate exactly the right amount of active video data.
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EECS150 Lab Lecture #8

19. Video Again ITU 601 Standard
The video camera follows the ITU 601 standard, which has 507 active lines.
Odd Field (262 Lines)
6 Vertical Blanking, 254 Active, 2 Vertical Blanking
Even Field (263 Lines)
7 Vertical Blanking, 253 Active, 3 Vertical Blanking
The provided video decoder sends video data order {Cb, Y, Cr, Y}.
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EECS150 Lab Lecture #8

20. Tips, Hints, & Common Pitfalls
Timing for writing is tricky. Recall from Checkpoint 1 that the black box puts data on the DQ line based only on WriteRequest timing. You’ll have to take care of this timing yourself now.
4/18/2019
EECS150 Lab Lecture #8

21. Tips, Hints, & Common Pitfalls
Make your arbiter design very clean
The lab specification states that most modules can be implemented in ¾ states.
You’ll need to extend your arbiter to accommodate four ports for Checkpoint 4.
Your encode and decode processors should be almost identical. They are basically the same module.
4/18/2019
EECS150 Lab Lecture #8

22. Tips, Hints, & Common Pitfalls
Long synthesis
Due to increased complexity of this checkpoint, putting your design on the board can take up to 10 minutes.
Avoid the vicious cycle of:
Changing one line
Generating the programming file
Fail
Repeat
If you catch yourself doing this, make ModelSim testbenches. Yes, you can simulate the blackbox FIFOs.
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EECS150 Lab Lecture #8

23. Questions?
4/18/2019
EECS150 Lab Lecture #8