1. PAC ISS
Zong-Cing Lin
PAS lab, CSIE, NTU

2. Outline Introduction PAC ISS Architecture Pipeline Instruction packet
PAS lab, CSIE, NTU

3. Introduction PACDSP: a VLIW DSP
High performance, low cost for multimedia applications.
Suitable for the products with multi-standard CODEC requirement.
PMP (portable media player)
Smart phone
TV controller
Low cost by VLIW
PAS lab, CSIE, NTU

4. Architecture
CFU: customized function in
PAS lab, CSIE, NTU

5. Pipeline Instruction Fetch Instruction Memory Access
One cycle latency to access the instruction memory
Instruction Dispatch
Dispatching the instructions of VLIW packet into the relative slots
Instruction Decode
PAS lab, CSIE, NTU

6. Pipeline (cont’d) Read Operand Execution 1 Execution 2 Execution 3
most datapath function unit
Execution 2
Multi-cycle instructions
Sending control signals to data memory
Execution 3
Processing data loaded from the data memory.
Register Write-back
PAS lab, CSIE, NTU

7. PSCU Program Sequence Control Unit
the controlling issues of the program flow.
dispatching instructions to the scalar unit and VLIW datapath.
In the speaking of pipeline architecture, it should bring PSCU under preceding 4 stages.
PAS lab, CSIE, NTU

8. Scalar Scalar unit Handling control-based task for PACDSP.
Simple capacity for data computing, like a RISC machine in PACDSP.
Main functions:
Program flow control function
Data processing function
Memory access function
Data transfer function
Register:
General purpose scalar register (R0-R15)
System register (SR0-SR15)
Predication register (P0-P15)
PAS lab, CSIE, NTU

9. VLIW datapath Two clusters; Four way Arithmetic Unit Load/Store Unit
Arithmetic and comparison instructions
Data transfer instructions
Bit manipulation instructions
Multiplication and accumulation instructions
Special instructions
Load/Store Unit
Arithmetic and comparison instructions
Data transfer instructions
Bit manipulation instructions
Load/Store instructions
Supporting double load/store instructions
Special instructions
稍微描述一下他們在第五個pipeline stage同時開工
但Load/Store Unit結束的時間可能會比較晚
PAS lab, CSIE, NTU

10. VLIW datapath (cont’d)
Register:
Ping-pong register file (D0-D7 & D8-D15)
Accumulator register (AC0-AC7)
Address register (A0-A7)
Constant register (C0-C7)
Control flags (CF0-CF7)
Ping-pong之名也許是因為au和ls可以讀寫不同group的register
PAS lab, CSIE, NTU

11. Instruction Packet Instruction slot Instruction types
PSCU / Scalar instructions 1
VLIW Load/Store Instructions (cluster 1) 2
VLIW Arithmetic Instructions (cluster 1) 3
VLIW Load/Store Instructions (cluster 2) 4
VLIW Arithmetic Instructions (cluster 2)
稍微提一下有提供instruction broadcast的功能 1、3和2、4
PAS lab, CSIE, NTU

12. PAC ISS Cycle-accurate instruction set simulator (ISS)
It can dump registers and memory contents cycle by cycle.
It can simulate more than cycles per second in average
PAS lab, CSIE, NTU

13. Execution Flow of PAC ISS (I)
Set the configure file of ISS to dump register or memory value.
See demo!!
Row
Meaning
Range
To dump the register of cluster 1 if it is set
1:dump; 0:don’t dump 1
To dump the register of cluster 2 if it is set 2
To dump the register of scalar if it is set 3
To dump the predicate & branch registers if it is set 4
To dump the control registers if it is set 5
To dump the data memory if it is set 6
The start address of dumped memory (in hex)
~0000fffe 7
The end address of dumped memory (in hex)
~0000ffff 8
To dump the constant register of cluster1 if it is set 9
To dump the constant register of cluster2 if it is set 10
The flag of boot standalone
No use now.
PAS lab, CSIE, NTU

14. Execution Flow of PAC ISS (II)
Options:
o: specify the input file is in ELF format (essential)
g: run ISS with GNU GDB
d: dump the registers and internal memory content cycle by cycle
s: step by step execution
r: display the registers content on stdout
m: display the internal memory content on stdout
PAS lab, CSIE, NTU

15. Execution Flow of PAC ISS (II) (cont’d)
Options:
l: set the memory model to interleaving mode
p: pre-load data into memory
c: show PC value in dump file
f: dump the final cycle content
i: specify the local memory size in MB
PAS lab, CSIE, NTU

16. Demo (I) See the basic information after simulation
Use file to check input file type
Options:
o specify the input file is in ELF format
Local memory size
PAS lab, CSIE, NTU

17. Demo (II) Options: s: step by step execution
r: display the registers content on stdout
o: specify the input file is in ELF format
PAS lab, CSIE, NTU

18. Demo (III) Dump cycle by cycle Options: c: show PC value in dump file
d: dump the registers and internal memory content cycle by cycle
o: specify the input file is in ELF format
PAS lab, CSIE, NTU

19. Demo (IV)
Run ISS with GDB
Options:
PAS lab, CSIE, NTU