1. ECE 352 Digital System Fundamentals
Register Design
In this presentation, we will look at how we go about designing registers.

2. Register Design
To design a register, we need to know what capabilities it should have
How big is it (how many bits)?
What should it reset to (if anything)?
What operations should it perform?
What control inputs does it have, and how do these signals indicate the register operations?
Does it need status outputs?
As with ALU design, the control inputs may be specified, or the designer may get to choose them in a way that simplifies the register design
Every design needs to start with a specification of exactly what the register’s capabilities need to be. We need to know how wide the register is, if it requires any asynchronous reset behavior, and what operations it has to perform. The specification must define the control inputs it has, and how those signals should be interpreted. If the register needs status outputs, we need to know what those outputs represent so we can create the required circuitry. If the control inputs are not specified, the designer should choose them to simplify the design of the register or the hardware that the register is connected to.

3. Specifying Register Capabilities
List the register operations it can perform
Also called microoperations or register transfers
We use a particular notation to describe operations on register values: DESTREG  EXPRESSION
DESTREG is the name of the destination register
EXPRESSION is what will be loaded into that register (e.g., a constant, the result of an operation, etc.)
An operation expressed in this notation is commonly referred to as a register transfer language (RTL) statement
The expression may be a logic or arithmetic operation
Note: we rarely (if ever) design registers capable of generic division or multiplication, because this circuitry is very large (particularly for division unless it is by a power of two)
As part of the specification, we list all the operations the register must perform. These register operations are commonly referred to as microoperations or register transfers. We describe the register transfers using a specific notation, which places the destination register on the left side of the arrow, and a description of what will be loaded into the destination register on the right side of the arrow. This form of expressing a register operation is commonly referred to as a register transfer language (or RTL) statement. You should already recognize the form of an RTL statement from assembly language – it is how we define what the instructions in an ISA actually do. The expression can be any logical or mathematical operation, but we generally do not design registers that are capable of complicated operations like multiplication or division—unless it is by a power of two, which is just a shift.

4. Example Register Operations
Description
R0  R1 + R2
Write the sum of the contents of registers R1 and R2 into register R0
A  A + 1
Increment the contents of register A
R3  ASR R4
Overwrite the contents of register R3 with the value in register R4 arithmetically shifted right by one bit (sign-extended)
Y  A + B
Write the bitwise OR of values A and B into register Y
Here we show some examples of RTL statements that each describe a register operation. Each RTL statement is accompanied by a plain language description to ensure that the RTL is interpreted correctly. Since we often use a plus sign to mean either addition or a logical OR, we need to ensure that is clarified in the description. These are just a few examples; we will use RTL statements to describe all register transfers.
These are just a few examples; there are many other possibilities!

5. Example Register Specification 1
64-bit register R with an asynchronous active-low clear input CLRN
Control Inputs
Operation
SHIFT
LOAD
Hold 1
Store IN into R
Shift R’s contents one position to the left
Undefined
Here is the complete specification for the register R that we looked at in the previous video. The specification tells us the meanings of the control inputs. If neither control input is asserted, the register holds its value. Note that the operation is undefined when both inputs are asserted – this has two implications. First, the circuit that uses the register must ensure that SHIFT and LOAD are never asserted simultaneously at the active clock edge, since the effect on the register is unknown. Second, from the designer’s point of view, this provides the opportunity to use a don’t-care condition to simplify the design. The two status outputs provide information about the current value held by the register; their meanings are also given in the specification. Finally, the register also has an active-low asynchronous clear input that forces the stored value to 0—in other words, it clears every flip-flop in the register.
Status Outputs
ODD
1 if R currently has odd parity (odd number of 1s), 0 otherwise
ZERO
1 if R contains all 0s, 0 otherwise

6. Example Register Specification 2
8-bit register Y with data inputs A and B
Control Inputs
Operation
RST
OP1
OP0
Y  Y 1
Y  Y x 2
Y  A + B
Y  A – B X
Y  0
Our second example register has two 8-bit data inputs and an 8-bit data output. This register does not have any asynchronous inputs. The control inputs are defined in a way that gives the synchronous reset priority over the two OP inputs. We use Xs to indicate all possible values of the OP inputs. Note that some operations use only the stored data, whereas others use the A and B inputs to update Y. The status outputs ZERO and NEG indicate whether the CURRENT value stored in Y is zero or negative. The VALID output indicates whether or not the PREVIOUS operation overflowed (resulting in an invalid current value). To implement the VALID signal, we will need to have an extra flip-flop whose input is the overflow signal from the internal logic, but only update the flip-flop when the register actually does an operation.
Status Outputs
VALID
0 if previous operation resulted in overflow, 1 otherwise
ZERO
1 if Y contains all 0s, 0 otherwise
NEG
1 if Y is negative, 0 otherwise

7. Register Design
Like an ALU, a register often requires similar functionality for some/all of its bits
We can design a register cell (one bit of the register) and replicate it to form the register
Saves time and effort!
Some bits of the register may require slightly different designs (such as the LSb and MSb), or the edge cells may have different connections
Also saves debug and verification effort
Test and debug the register cell (a small design)
Test the connections between register cells (a limited part of a large design)
We approach register design in a similar manner to designing an ALU. We can design a register cell and replicate it to match the register width, allowing us to design at a much smaller scale. As with the ALU, we may need more than one cell design, or we may be able to use the same design but make different connections to the edge cells. In addition to saving design effort, this also greatly simplifies testing the register. We start by testing the register cell. Since it is a small design, testing it is relatively easy. Then, when we test the complete register, we only need to test the connections between cells, and not the functionality of the cells themselves. This results in a much simpler test of the register, and a reduction in overall test time and effort.

8. Design Procedure Determine required data inputs
Determine required control signals
If control signals not predetermined, you get to choose which values cause which operations!
If possible, choose these to simplify the design
Determine internal structure based on needed operations and control signals
Determine if register cells will share a common design or if different design(s) are needed at different bit positions
Create each required unique cell design
Place instances of cell, and interconnect as required to complete the register implementation
Let’s review a generalized register design procedure, assuming that the required register capabilities have already been specified. First, determine the required data inputs to the register. This will depend on the number of outside operands that are involved in the register operations. If the control signals were not specified, determine how many different things the register can be commanded to do, and from that derive a set of control signals to differentiate between them. Of course, we would want to choose signals and values in a way that simplifies the register design. Next, look at how many types of cells will be needed to implement the register. As in ALU design, we look at how operations occur at the register level to determine the communication requirements between cells, then use that information when we design the required cell(s). Finally, place the number of cells required by the register, and interconnect them as required.

9. Register Design Example
3-bit version of register Y from previous example
Without the status outputs…
Control Inputs
Operation
RST
OP1
OP0
Y  Y 1
Y  Y x 2
Y  A + B
Y  A – B X
Y  0
For example, assume we are designing register Y to implement the specified operations, but without any status outputs for now.

10. Register Design Example
Here we’ve used a flip-flop with built-in synchronous reset, so the reset input is connected directly to each flip-flop. The value to be stored in each bit position’s flip-flop is selected by a 4-to-1 mux that uses OP1 and OP0 as its select inputs. When the 2-bit OP signal is 00, the register holds, so we reload the flip-flop with its current value. When OP is 01, the register shifts left, so we load each flip-flop with the value stored in the cell to the right, filling with 0 at the least-significant bit.
When OP1 is 1, we either add or subtract. OP0 is 0 when we add, and it is 1 when we subtract. So we augment a ripple-carry adder to become an adder/subtractor, and for those two modes the input of each flip-flop is the output of its associated full adder.
In this example, we have intentionally done the register design as a single unit so we can illustrate different ways that the design could have been partitioned.
Control Inputs Op
RST
OP1
OP0
Y  Y 1
Y  Y x 2
Y  A + B
Y  A – B X
Y  0

11. Register Design Example
Several ways to create the design hierarchy…
ALU cells with flip-flops on their outputs
There is more than one way to partition this design. One way we could have designed it is to first create an ALU cell design, replicate it,

12. Register Design Example
Several ways to create the design hierarchy…
ALU cells with flip-flops on their outputs
and then place a flip-flop on the output of each ALU cell.

13. Register Design Example
Several ways to create the design hierarchy…
ALU plus storage register
Alternately, we could group the ALU cells into an ALU, and combine the flip-flops to create a separate storage register.

14. Register Design Example
Several ways to create the design hierarchy…
ALU plus storage register
We would then connect the ALU and storage register. Note that in this case, the storage register updates every cycle to the value output by the ALU, so for the “hold” mode, the ALU needs to output the value it receives from the register. Instead, we might use a storage register with enable, and only enable the register to update when doing an operation.
Note: Y is an output of the register, and an input to the ALU (for Y  Y and Y  Y x 2)

15. Register Design Example
Several ways to create the design hierarchy…
Register cells
Yet another design method would be to group the logic and flip-flop at each bit position into a register cell,

16. Register Design Example
Several ways to create the design hierarchy…
Register cells
and then create an operational register from those register cells.

17. Which Design Is Correct?
It depends…
The ALU plus register method is best if…
The ALU output is the input to multiple registers
We will discuss this more in another lecture
The ALU itself would be constructed of ALU cells
You already have previously-debugged ALU and registers with the right capabilities available to you
Why redesign them?
The register cell version is best otherwise
May design an ALU cell inside the register cell…
Want to balance design effort and reusability
As in most things, determining the best approach is often complex and depends on many factors. If the ALU is a shared resource that we want to use with multiple registers, then partitioning into an ALU plus register is probably the best choice. Or, if we already have an ALU design with the required capabilities, it’s probably a good idea to reuse that and add a register. For other designs, the operational register version is probably best. The whole point is to find a good balance between design effort, reusability, and any other constraints that impact the design.

18. Adding Status Outputs
Sometimes the status outputs are functions of the flip-flop outputs…
NEG and ZERO outputs of example register Y
ODD and ZERO outputs of example register R
Sometimes we need to add extra storage to keep track of the status also…
VALID output of example register Y
Based on whether or not the register operation had overflow
This cannot be detected by looking at the only the contents of the register…
Registers often have status outputs that indicate some key information about the value stored in the register or its recent operations. The status output circuitry may simply be combinational logic functions of the current register value, such as the NEGative and ZERO outputs on register Y. The outputs can also be used to indicate something about a previous operation, such as the VALID output of register Y that indicates if the current Y value is valid, or if an overflow had occurred and so it is not valid. We cannot detect overflow by just looking at the stored result. We must have logic that detects if an operation causes overflow, and we need to store that flag into a separate flip-flop inside the register when we store the result of the operation.

19. Notes About Control Signals
Our two example registers used two different design philosophies with the control signals
unencoded
unencoded
encoded
Control Inputs
Operation
SHIFT
LOAD
Hold 1
Store IN into R
Shift R’s contents one position to the left
Undefined
Control Inputs
Operation
RST
OP1
OP0
Y  Y 1
Y  Y x 2
Y  A + B
Y  A – B X
Y  0
We can take two fundamentally different approaches when designing the control signals for a register. We can use unencoded signals, as are used with register R. In this case, each signal represents a specific operation, and it is assumed that only one of the signals will ever be asserted at one time. For this reason, we sometimes refer to this as one-hot signaling. The advantages to this method are that it may be simpler to generate the signals in the control unit, and not needing to decode the control signals can sometimes make the register design simpler. Alternatively, we can encode the operations into a smaller number of signals, as we did for register Y. Since we have four operations plus reset, we need three signals. We thus encode the four operations into a 2-bit value, plus an unencoded reset signal. The advantage to encoding the control signals is the smaller number of connections required between the control unit and the register. If the signals are intelligently encoded so that operations with similar needs have similar codes, it may also help simplify some of the register design.

20. Notes About Control Signals
Remember that a register is a set of flip-flops, (possibly with some additional logic)
The register updates on the active clock edge, based on the data and control inputs values it has just before that clock edge
The control signals are generated by an FSM which uses the registers to perform some task
Based on the current status of registers and other inputs, the FSM commands the registers to perform various operations
The type of FSM output will determine how quickly it can react to the situation and command an operation
Let’s talk more about control signals, and specifically, their timing. A register is essentially flip-flops plus some logic, so any changes to the register’s stored value will not occur until the clock edge AFTER it is commanded to do an operation. The register’s control signals are normally generated by a control unit, which is an FSM. An FSM can be designed with Moore or Mealy outputs, which affect how quickly its output(s) can react. Let’s look at an example to see how this works.

21. Control Signal Timing
A register stores the time when the “NOW” button is pressed
In the circuit shown, the TIME signal is the output of a free-running 32-bit counter. In other words, it counts up by one every cycle. The signal NOW comes from an active-high pushbutton. An edge detector FSM detects when the button is pressed, and causes the register to store the current time. We’ll assume that all flip-flops in the state machine and register are positive-edge triggered by the same clock.
Let’s look at what happens if the button is pressed in the middle of the clock cycle when TIME equals 1000.

22. Control Signal Timing - Mealy
Assume a Mealy edge detector
First, we’ll look at what happens if the edge detector is a Mealy machine. When the button is pressed, the Mealy machine output reacts immediately, and commands the register to LOAD. At the next clock edge, the register loads the current TIME value, which is The same clock edge that makes the register load a new value in response to the LOAD signal also causes the LOAD signal—the output of the Mealy state machine—to go to 0.
As you can see, the register updates to hold the current value of the timer at the time the button was pressed.

23. Control Signal Timing - Moore
Assume a Moore edge detector
Now, let’s look at what happens if the edge detector is a Moore machine. When the button is pressed, the Moore machine can’t react immediately, since it needs to change states in order to change its output—which can only happen at an active clock edge. So the clock edge AFTER the button is first pressed, the edge detector changes state and its output goes to 1. This commands the register to LOAD.
However, the register cannot react until the NEXT clock edge, so the register’s stored value will be One cycle after the button press, the register stores the current value of the timer. But since it is one cycle later, the timer has counted one further since the button press. This may seem like a small difference, but “off by 1” errors can be a serious problem. Even when they’re not, the extra delays can cause a machine to be much slower than necessary. These are important reasons to use Mealy outputs on control units that generate signals to control registers.

24. ECE 352 Digital System Fundamentals
Register Design
This concludes our video on other flip-flop types and their use in FSM design.