1. WELCOME TO EE457 COMPUTER SYSTEMS ORGANIZATION

2. THREE MAIN TOPICS 1. CPU DESIGN 2. MEMORY SYSTEM 3
THREE MAIN TOPICS 1. CPU DESIGN 2. MEMORY SYSTEM 3. COMPUTER ARITHMETIC 4. Advanced CPU design topics

3. CPU DESIGN MICRO-ARCHITECTURE DESIGN GENERAL DIGITAL SYSTEM DESIGN

4. MEMORY SYSTEM DESIGN CACHE + VIRTUAL MEMORY

5. COMPUTER ARITHMETIC 2’s Complement Arithmetic Review FAST ADDERS (CLA) FAST MULTIPLIERS NON-LINEAR PIPELINES FOR ARTHMETIC OPERATIONS

6. COURSE PRE-REQUISITES EE354L(Previously called EE254L/201L) INTRODUCTION TO DIGITAL CIRCUITS Knowledge of some assembly language USC undergraduates have learnt picoblaze ASM

7. LECTURES & DISCUSSIONS LECTURES:. (a) 12:00-1:50PM TTh OHE230
LECTURES & DISCUSSIONS LECTURES: (a) 12:00-1:50PM TTh OHE (b) 5:00-6:50PM TTh OHE136 DISCUSSIONS: (a) 03:30-04:20PM Th ZHS252 (b) 12:00-12:50PM F OHE122

8. EXAMINATIONS (a) Quiz (~10%) Thursday Feb
EXAMINATIONS (a) Quiz (~10%) Thursday Feb. 7, :00 - 8:00 PM PST (b) Midterm (~24%) Thursday Mar. 21, :00 - 8:00 PM PST (c) Final (~33%) Wednesday, May 7, 2019 Two time slots 3:30-6:30 PM or 4:30-7:30 PM PST The official time slot of 4:30-6:30 is extended by 60 Min. Please help me and the class by agreeing to the exam times. Thanks!

9. COURSE WEIGHTS

10. LATE PENALTY HOMEWORKS:
LATE PENALTY HOMEWORKS: UP TO 5% PER DAY IF SOLUTION IS NOT DISTRIBUTED

11. LATE PENALTY LABS: 3% flat penalty for 3 days late

12. LECTURE CLASS ATTENDANCE PENALTY FOR MISSING:. 1% FOR 4th AND 5TH
LECTURE CLASS ATTENDANCE PENALTY FOR MISSING: 1% FOR 4th AND 5TH 2% FOR 6TH AND AFTER PENALTY FOR MISSING DISCUSSION CLASS: HALF OF LECTURE CLASS MISSING PENALTY % FOR 4th AND 5TH 1% FOR 6TH AND AFTER

13. REMOTE STUDENTS gandhi@usc.edu

14. DESIGN PROJECTS. PARTIALLY COMPLETE DESIGN FILES
DESIGN PROJECTS PARTIALLY COMPLETE DESIGN FILES Core design Verilog file: ~50% complete Testbench and wave.do files: ~80% to 100% complete TTL DATABOOK  NOT NECESSARY

15. Esperan Verilog Reference Guide
Is posted on the BB for personal use of USC faculty and students.

16. IEEE Verilog standard ieee-1364-2001 for USC library members only -- please do not distribute

17. HOMEWORK:. INDIVIDUAL EFFORT LAB:
HOMEWORK: INDIVIDUAL EFFORT LAB: (1) VERILOG CODING, SIMULATION AND DEBUGGING TEAM EFFORT (2) JUSTIFICATION, END-OF-LAB QUESTIONS INDIVIDUAL EFFORT

18. CLASS WEBPAGE DEN D2L (Desire 2 Learn) https://courses. uscden
CLASS WEBPAGE DEN D2L (Desire 2 Learn) LEC / DIS WEBCASTS ASSIGNMENTS ANNOUNCEMENTS OFFICE HOURS

19. Verilog language and ModelSim Simulator INTRO. LECTUREs are posted

20. Buy these two items from the Bookstores (1) TEXTBOOK Computer Organization & Design - The Hardware and Software Interface 5th edition (or 4th edition (Revised Printing)) By D. A. Patterson (Berkeley) and J. L. Hennesy (Stanford) (2) CLASS NOTE available online, but better to buy the paper copy so that you can write-on ========================================= Lab Manual .pdf files will be posted progressively on the BB

21. Understand, No need to memorize, Learn to design
Understand, No need to memorize, Learn to design. Demonstrate your understanding in the exam ~14 hours of office hours per week

22. Grades

23. Grades
Very easy to get an A grade

24. Grades
Very easy to get an A grade
Equally easy to get a F grade

25. Grades of Fall 2018

26. Two scales used in in Fall 2018 to divide scores between Final exam and the earlier exams

27. We appreciate your efforts
~ 50% of the class gets an A grade
No place for the lazy and uninterested
~10% of the class fails or drops

28. There is no competition. Everyone can get an A grade
There is no competition. Everyone can get an A grade. You need to aspire for it, and work for it. You get what you worked for. No grace grade (No minimum grade).

29. Undergraduates Please do not take it easy
First five weeks, in the RTL design area, you have an advantage.
But in the remaining 10 weeks, if you slacken, you end up with a C or a D 

30. Academic Integrity Very Important Do not take it easy
You can work with your lab partner on labs
Homeworks and lab reports are individual effort items
Do not copy lab codes. You can easily get caught!
We are here to help, so there is no need to cheat.

31. Download the lab exercises and work on them
Download the lab exercises and work on them. Do not get them from your seniors