1. Christian Hackmann and Evert Nord
AM-Demodulator
Outline:
Christian Hackmann and Evert Nord
proudly
presents:
Introduction
Requirements
Band-pass
Low-pass
Threshold
VHDL-Design
Matlab
Results
The ”AM-Demodulator”

2. AM-Demodulator Outline: Introduction Requirements Band-pass Low-pass
Threshold
VHDL-Design
Matlab
Results

3. AM-Demodulator Outline: A threshold-value should be controlled
from a micro-controller
This requires a Wishbone-interface
Everything should be implemented on
a FPGA
It should work with a minimum frequency
of 100 MHz
It should handle the bitrates:
10 kBits/sec.
40 kBits/sec.
80 kBits/sec.
Outline:
Introduction
Requirements
Band-pass
Low-pass
Threshold
VHDL-Design
Matlab
Results

4. AM-Demodulator Outline: Introduction Requirements Band-pass Low-pass
Threshold
VHDL-Design
Matlab
Results
To get the right signal
FIR-filter
3:rd order
fcenter = 13 MHz
fcutoff1,2 = 13 MHz ± 0,2 MHz

5. AM-Demodulator Outline: Introduction Requirements Band-pass Low-pass
Threshold
VHDL-Design
Matlab
Results
For smoothing out the signal
Moving average
FIFO-register
Size 8

6. AM-Demodulator Outline: Introduction Requirements Band-pass Low-pass
Threshold
VHDL-Design
Matlab
Results
To decide if the signal is a 0 or 1

7. AM-Demodulator Outline: Introduction Requirements Band-pass Low-pass
Threshold
VHDL-Design
Matlab
Results
The Toplevel design has:
8-Bit parallel input
1-Bit serial output
communication with a microcontroller

8. AM-Demodulator Outline: Introduction Requirements Band-pass Low-pass
Threshold
VHDL-Design
Matlab
Results
Simulation with Matlab
GUI for comfortable testing
Good help for VHDL-modelling

9. AM-Demodulator Outline: Coefficients from Matlab
 Transformed into fixed point (17-Bits)
For each tap one coefficient is multiplied
with the 8-Bit input
Adding each tap to the output
Outline:
Introduction
Requirements
Band-pass
Low-pass
Threshold
VHDL-Design
Matlab
Results

10. AM-Demodulator Outline: Introduction
Requirements
Band-pass
Low-pass
Threshold
VHDL-Design
Matlab
Results
Pushes the input-signal through a register
The input is added to the sum of the
content of the register and the last element
is substracted
Getting the average by dividing with the
register size

11. AM-Demodulator Outline: Introduction Requirements Band-pass Low-pass
Threshold
VHDL-Design
Matlab
Results
The average is just compared with a
threshold value
Serial output

12. AM-Demodulator Outline: Introduction Requirements Band-pass Low-pass
Threshold
VHDL-Design
Matlab
Results
Successful verification of the design with
Modelsim and Xilinx Project Navigator
The maximum design frequency is
MHz
Wishbone interface is implemented in
design

13. Thank YOU for listening!!!
AM-Demodulator
Thank YOU for listening!!!
Questions
are
Welcome!
Evert & Christian