1. Hazard-free Karnaugh Map Minimisation
EE19D Digital Electronics I
(Supplement note )
Hazard-free Karnaugh Map Minimisation
Objective: Analyses logic design for glitch-free operation
Dr Brian Copeland/UWI

2. B  A’; Z=B=A’ ONLY in steady state
Engineers must often take account of non-idealities in logic devices that cause problems in minimum cost logic circuit. One serious problem is caused by signal delays in the components used to implement the design. This is most critical for the inverters that may be used at the input of 2-level AND/OR or OR/AND topologies. Z B A A Z d
IDEAL INVERTER
REAL INVERTER A A 1 1 B 1 B 1 Z 1 d
B  A’
B  A’; Z=B=A’ ONLY in steady state
Dr Brian Copeland/UWI

3. Example: In an ideal circuit F should remain 1 for B=0, C=1, and A : 1,0,1. The nonideal inverters produce a glitch when the input changes from 1-0, however. BC A B C F Z
101 1 X Y 00 01 11 10 1 A
F = AB’ + A’C A Z X Y F
glitch d
Dr Brian Copeland/UWI

4. Definitions: A logic hazard is a condition under which a combinational circuit is susceptible to transient output error as a result of a change in input.
Definitions: A static 1 (0) hazard is a condition under which a combinational circuit outputs a temporary logic 0 (1) when its output should have remained at logic 1 (0) in response to a change in one input variable.
Definitions: A dynamic hazard is a condition under which a combinational circuit output alternates between 0 and 1 at least once before settling to its final steady state in response to a change in one input variable.
Static 1
Static 0
Dynamic
Combinational circuit outputs are functions only of the present circuit inputs
Sequential circuit outputs are functions of present as well as past circuit inputs i.e. the circuit has memory
Dr Brian Copeland/UWI

5. Circuit with Logic Hazard
Hazards may or may not deleterious to circuit operation: They are deleterious if the network to which the circuit with a hazard is connected is fast enough to perceive the output glitch as a valid input transition on which action is to be taken. An example is the clock input of a sequential logic device:
Logic counter
QDQCQBQAQDQCQBQA+1
On each positive transition of CLK
“positive edge triggered”
Circuit with Logic Hazard
CLK 1
CLR LD 1 P T
The glitch is of nanosecond duration and is therefore not observed by a human observer but does appear as a “clock tick” to the counter.
74LS163 D QD QC QB QA
Dr Brian Copeland/UWI

6. Consider transition: ABC:101011. Possible transition paths:
For now we will only analyse situations where hazards are induced by a change in only one input.
Rationale: Glitches are unavoidable when attempts are made to change >1 input simultaneously (a pathological situation). In the case of two inputs, for example, one signal will change before the other with probability 1. Engineering reliability is compromised by the fact that we may never know which one changes first. BC 00 01 11 10 1 BC 00 01 11 10 1 A A
F = AB’ + A’C
no glitch
Consider transition: ABC:101011.
Possible transition paths:
ABC: 101011
ABC: 101001 011 (A “faster”)
ABC: 101111 011 (B “faster”) BC 00 01 11 10 1 A
glitch
Dr Brian Copeland/UWI

7. In fact…..
The two level AND/OR (or NAND/NAND) topology is susceptible to static-1 hazards but NOT to static 0 hazards
The two level OR/AND (NOR/NOR) topology is susceptible to static-0 hazards but NOT to static 1 hazards
The two level OR/AND (NOR/NOR) and OR/AND (NOR/NOR) topologies are NOT susceptible to dynamic hazards
Dr Brian Copeland/UWI

8. Static 1 hazards can be eliminated by ensuring that all adjacent minterms are covered by a common product term.
NOTE: This means that minimum logic may require the addition of extra product terms to eliminate hazards
Rationale:
A glitch can NEVER be experienced when moving between minterms covered by one product term. This is because the corresponding product term inputs are fixed over the minterms it covers; by definition only those variables not included in the product term (i.e. those eliminated) can be varied. A B C F Z
101 1 X Y BC 00 01 11 10 1 A
F = AB’ + A’C
For ABC: 100101 only C changes. The transition occurs over cells covered by the product term AB’ which maintains output 1, keeping F at 1
Dr Brian Copeland/UWI

9. F is “clamped” at the correct value by the new gate
Example: New implicant, B’C, added to cover minterms with hazard inducing transitions
101 A BC X 00 01 11 10 1
F=1 B A Z Y
F = AB’ + A’C C 1 1 W A Z X Y
F,W
F is “clamped” at the correct value by the new gate
Circuit is now not minimum
Dr Brian Copeland/UWI

10. Minimum Hazard-free design (AND/OR)
Design the minimum logic realisation as before, selecting the minimum number of prime implicants to cover the 1-cells
Identify on the Kmap, all the adjacent minterms that are not covered by a common prime implicant.
Add as few extra prime implicants as possible to cover these adjacent pairs
PIs:
EPIs:
Minimum Cover:
Hazard-free minimum:
Example CD 00 01 11 10 1 AB
Dr Brian Copeland/UWI