1. Recording Synthesis History for Sequential Verification
Robert Brayton Alan Mishchenko
UC Berkeley

2. Overview Introduction Recording synthesis history
Retiming
Combinational synthesis
Merging sequentially equivalent nodes
Window-based transformations
Transformations involving observability don’t-cares
Using synthesis history
Technology mapping
Verification
Experiments
Conclusions

3. Introduction
Sequential synthesis promises to substantially improve the quality of hardware design
Efficient verification is needed to ensure wider adoption
Sequential equivalence checking without history is in general PSPACE-complete [Jiang/Brayton, TCAD’06]
But synthesis history can make sequential equivalence checking linear or “close to linear” in circuit size
The focus of this presentation
recording a type of synthesis history
using it for sequential equivalence checking

4. Sequential AIGs Combinational AIG Sequential AIG
Boolean network of 2-input ANDs and inverters
Combinational structural hashing
Sequential AIG
Registers are considered as special type of nodes
Each register has an initial state (0, 1, or don’t-care)
Sequential structural hashing [Baumgartner/Kuehlmann, ICCAD’01]
Simplified sequential AIG
Combinational AIG with registers as additional PIs/POs
In this work we use simplified sequential AIGs

5. Sequential Synthesis Combinational rewriting Retiming
Register sweeping
Detecting and merging seq. equivalent nodes
Circuit optimization with approximate unreachable states as external don’t-cares
Sequential rewriting

6. Recording Synthesis History
Two AIG managers are used
Working AIG (WAIG)
Structural hashing is used
History AIG (HAIG)
Structural hashing is not used
Two node mappings are supported
Every node in WAIG points to a its copy in HAIG
Some nodes in HAIG point to other nodes in HAIG that are believed to be sequentially equivalent as a result of synthesis performed in WAIG
WAIG
HAIG

7. WAIG and HAIG
WAIG
New logic nodes are added as synthesis proceeds
Old logic cones are replaced by new logic cones and removed
The fanouts of the old root are transferred to be fanouts of the new root
Nodes without fanout are immediately removed
Maintains accurate metrics (node count, register count, logic depth)
HAIG
As each new node is created in WAIG, a copy is found or is created in HAIG,
A link between them is established
Old logic cones are not removed
Fanouts are not transferred
Links between the HAIG nodes are established
Each time a node replacement is made in WAIG, the corresponding nodes are linked as sequentially equivalent in HAIG

8. Recording History for Retiming
WAIG
HAIG
Step 1
Create retimed node
copy
Step 2
Transfer fanout
Add pointer
Step 3
Recursively remove old logic
continue building new logic
Backward retiming is similar

9. Recording History with ODCs
When synthesis is done with ODCs, the resulting node is not equivalent to the original node
In HAIG, equivalence cannot be recorded
However, there always exists a scope, outside of which functionality is preserved, e.g. a window.
equivalence in HAIG can be recorded at the output boundary of this scope

10. Sequential Rewriting History AIG Sequential cut: {a,b,b1,c1,c}
Sequentially
equivalent
History AIG after rewriting step.
The History AIG accumulates sequential equivalence classes.
new nodes
History AIG
rewrite
Rewriting step.

11. Using HAIG for Equivalence Checking
Sequential depth = 1
Sequential depth of a window-based sequential synthesis transform is the largest number of registers on any path from an input to an output of the window
Theorem 1: If transforms recorded in HAIG have sequential depth no more than one, the equivalence classes of HAIG nodes can be proved by simple induction (k=1) over two time-frames
Theorem 2: If the inductive proof of HAIG succeeds in proving all equalities, then
the original and final designs are sequentially equivalent A A’ B B’ 1
unsat #1 #2
HAIG2
HAIG1

12. Conceptual Picture of HAIG
outputs
outputs B
Actually B is really smeared throughout the HAIG B
Registers and PIs
HAIG is simply a sequential circuit with lots of nodes that are disconnected or redundant. It contains initial circuit A and final circuit B. There are many suggested equalities.
If we prove all suggested equalities, then A=B sequentially.

13. Inductive Proof (k = 1) A B A B A Speculative reduction outputs
Second time frame A
outputs B
outputs A
Speculative reduction =
First time frame
Registers and PIs

14. Discussion
Typical criticisms of verification using a synthesis history
incorrect information may be passed from a synthesis tool to a verification tool
the same bugs may exist in both tools, canceling each other out
both situations may lead to a false positive
In the proposed methodology, history is a set of hints
Every step recorded must be proved by a different prover
The inductive prover in HAIG-based verification is simple
A HAIG prover in ABC (w/o AIG package and SAT solver) is simple
about 100 lines of code, compared to 2000 lines in a general prover
Can be written by independent person easily
The absence of counter-examples ensures fast runtime
A counter-example would be extremely rare and would point directly to an incorrect implementation of a synthesis transformation

15. Experimental Setup
Benchmarks are 20 largest public circuits from ISCAS’89, ITC’97, and Altera QUIP
Only 14 are shown in the tables below
Runtimes are in seconds on 4x AMD Opteron 2218 with 16GB RAM under x86_64 GNU/Linux
One core was used in the experiments
Synthesis includes three iterations of the script:
Balancing is algebraic tree restructuring for minimizing delay
Rewriting stands for one pass of AIG rewriting
Retiming consists of a fixed number of steps of forward retiming (at most 3000 retiming moves were performed in each iteration)
This script was selected to make the resulting networks hard to verify (Jiang/Hung, ICCAD ’07)

16. Synthesis Results Synthesis size and HAIG size

17. Comparison of verification times
Entry indicates a timeout at 1000 seconds. Timeouts are counted as 1000 seconds in runtime ratios.

18. Conclusions Motivated the use of synthesis history in SEC
Presented history recording using 2 AIG managers
Experimentally evaluated the use of history in Sequential Equivalence Checking
Confirmed savings in runtime
Confirmed reliability

19. Leave a trail of bread crumbs.