1. The ATLAS LAr. Calibration board K. Jakobs, U. Schaefer, D. Schroff
N. Dumont-Dayot, G.Ionescu, N.Massol, G.Perrot, P.Perrodo, I. Wingerter-Seez
LAPP, France 
C. de La Taille, N. Seguin-Moreau, L. Serin
LAL, France 
K. Jakobs, U. Schaefer, D. Schroff
Mainz, Germany
ATLAS
09/30/03
Nicolas Dumont Dayot-LECC2003

2. Nicolas Dumont Dayot-LECC2003
Contents
The Calibration board in the electronics chain.
Requirements
Principle.
The digital part.
Prototype with DMILL Asics.
Pulse shape.
DC, Pulse uniformity and linearity.
Timing and jitters uniformity.
Conclusion.
09/30/03
Nicolas Dumont Dayot-LECC2003

3. The Calibration board in the electronics chain
Timing Trigger Control
FRONT END ELECTRONICS
Pulsers
DAC
Calibration Board (130 )
DETECTOR
BACK END ELECTRONICS
E =  ai (Si - PED)
E  =  bi (Si - PED)
2 =  (Si - PED - E gi) 2
ANALOG
MEMORY
(SCA)
12 Bits
ADC
DSP
1600 Optical GLINK links
Shaper
Front End Board
Read Out Driver
09/30/03
Nicolas Dumont Dayot-LECC2003

4. Nicolas Dumont Dayot-LECC2003
Requirements
Goal: Inject a precision voltage pulse as close as possible as the physics pulse.
Outputs: 128 analog channels.
Rise time < 1ns, decay time around 400 ns .
Dynamic range : 16 bits (2 μA to 200mA) .
Integral non linearity < 0.1% .
Uniformity between channels < 0.25% .
Timing between physics and calibration pulse ±1ns.
Radiation hardness: 100 Krad, 1013 Neutrons (DMILL Asics).
Run at a few kHz.
09/30/03
Nicolas Dumont Dayot-LECC2003

5. Principle Pulser principle: Analog part simplified schematics:
I=2 μA to 200mA
V=100 μV to 5V
Room temperature
Liquid Argon
16 bits DAC
Voltage follower
Voltage to current conversion
09/30/03
Nicolas Dumont Dayot-LECC2003

6. Nicolas Dumont Dayot-LECC2003
The digital part
Slow control: through I2C bus.
Enable desired channels: ASICs REG0-3 (32 bits output registers).
Load DAC value: ASIC DAC REG (16 bits output register).
Delay calibration command: ASICs Delay0-1 (0-25ns ; step 1ns).
Synchronous commands: through TTCrx.
TTCrx decoding: ASIC TTC decode (calibration command).
09/30/03
Nicolas Dumont Dayot-LECC2003

7. Prototype with DMILL Asics (Nov 2002)
8x8 Op Amps pulsers
Channels <63-0>
DAC
TTCrx
Channels <127-64>
Power connector
09/30/03
Nicolas Dumont Dayot-LECC2003

8. Nicolas Dumont Dayot-LECC2003
Pulse shape
Study over the full DAC range (100μV-1V) on 1 channel.
Rise time < 2ns (small variation with DAC).
HF ringings at small DAC value (inductance package).
Parasitic Injected Charge
Small signal when DAC=0.
Due to pulser Cgs parasitic capacitance.
Equivalent to DAC=15μV at the max. of the signal.
Dynamic range of (1V/ 15μV).
DAC=100 µV
DAC=1mV (0dB)
DAC=10 mV (0dB)
DAC=0.1V (-20dB)
DAC=1V (-40dB)
09/30/03
Nicolas Dumont Dayot-LECC2003

9. Nicolas Dumont Dayot-LECC2003
DC uniformity
Study for a 10mV DAC value.
Measurements of the DC current of the 128 channels.
Instrument: 16 bits multimeter.
Before Operational Amplifier Offset correction
Mean = μA
RMS = 6.17
σ = 0.31%
After Operational Amplifier correction
Mean = μA
RMS = 1.04
σ = 0.05%
DAC voltage well distributed all over the board.
σ = 0.31% before offsets correction
σ = 0.05% after offsets correction
Even channels: blue and red plot.
Odd channels : green and yellow plot.
09/30/03
Nicolas Dumont Dayot-LECC2003

10. Nicolas Dumont Dayot-LECC2003
Pulse uniformity
Study after shaping (CRRC2 50 ns) for a 10mV DAC value
Instrument: 12 bits ADC sampling the signal at the peak.
σ =0.33%.
Pulse and DC uniformity well correlated.
09/30/03
Nicolas Dumont Dayot-LECC2003

11. Nicolas Dumont Dayot-LECC2003
DC & pulse linearity
Shaper gain=100
+0.05%
-0.05%
DC linearity residuals Pulse linearity residuals
Measurements on 3 gains (1,10,100)
DC linearity in black.
Pulse linearity in red.
Both linearity within ± 0.05%.
Dynamic and DC performances at the same level.
Shaper gain=10
+0.05%
-0.05%
DC linearity residuals Pulse linearity residuals
Shaper gain=1
-0.05%
+0.05%
DC linearity residuals Pulse linearity residuals
09/30/03
Nicolas Dumont Dayot-LECC2003

12. Nicolas Dumont Dayot-LECC2003
Timing uniformity
Study of the delay between channel0 and the others
Measurements for a 30mV DAC value.
Instrument: scope (1GHz analog bandwidth, 16Gsa/s).
1.2ns dispersion inside Op Amp rows (common calibration command to 8 Op. Amp.).
Small dispersion between rows (calibration lines not exactly equalized in lengths).
This will be corrected in the next prototype layout.
09/30/03
Nicolas Dumont Dayot-LECC2003

13. Jitters study Values below the 100ps expected.
Jitters between TTC clock (TTCvx) and calib. pulse
Instrument:
Scope (1GHz analog bandwidth, 16Gsa/s).
Histogram recording.
Scanning TTCrx fine delay (0-24 ns ; step 104ps)
jitters within ps.
Scanning Delay ASIC coarse delay (0-24 ns ; step 1ns)
jitters within ps.
Values below the 100ps expected.
09/30/03
Nicolas Dumont Dayot-LECC2003

14. Nicolas Dumont Dayot-LECC2003
Conclusion
Prototype built with DMILL Asics (November 2002).
Electrical measurements (uniformity, linearity) done.
Timing measurements (uniformity, jitters) done.
Front End Crate prototype installation done (March 2003).
Final prototype expected soon (October 2003).
Production of 130 boards will start spring 2004.
09/30/03
Nicolas Dumont Dayot-LECC2003