1. Copyright 2006 - Joanne DeGroat, ECE, OSU
Project Step 4
Step 1 in transitioning to behavioral modeling. We will wire behavioral code 1-to-1 with our gate level model.
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Copyright Joanne DeGroat, ECE, OSU

2. Copyright 2006 - Joanne DeGroat, ECE, OSU
Project Step 4
This is the start of the transition to behavioral modeling.
At the gate level you are near 1-to-1 with the hardware that is implemented
At the behavioral level you have a physical interface and then the function between.
1/8/ L7 Project Step 3
Copyright Joanne DeGroat, ECE, OSU

3. Copyright 2006 - Joanne DeGroat, ECE, OSU
VHDL view of the world
The VHDL view is one that starts with the interface. How do you connect to the world.
After this, you have the ARCHITECTURE which tell you what actions, responses, operations and transformations happen within the interface.
Many designers first think about what the function is, and, after the function is described what the interface is.
In the VHDL world you must first define the format, timing, frequency, etc. of how the data arrives and is output first.
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Copyright Joanne DeGroat, ECE, OSU

4. Copyright 2006 - Joanne DeGroat, ECE, OSU
Thus Far
Have described the ALU architecture structurally using 2 basic components described at the gate level. Very close to a 1-to-1 representation of the gates.
Now will start a transition to a behavioral description where we raise the level of abstraction each time.
1/8/ L7 Project Step 3
Copyright Joanne DeGroat, ECE, OSU

5. Straight algorithmic representation of the slice
Will use a process with a loop. Each iteration of the loop will move to the next most significant slice.
On the first iteration will compute the P operation, then the K operation, do the logic function of the carry block, and then finally the results block.
Naturally fits into a loop.
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Copyright Joanne DeGroat, ECE, OSU

6. Example of what I am talking about
Consider the bit-sliced comparator
Now lets do it slice-by-slice algorithmically
Start by writing the multi-bit entity
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Copyright Joanne DeGroat, ECE, OSU

7. The Entity and start of Architecture
ENTITY byte_comparator IS
PORT (a,b : IN bit_vector (7 downto 0); --a & b data
gt,eq,lt: IN bit; --previous slice results
a_gt_b, a_eq_b, a_lt_b : OUT bit); --outputs
END byte_comparator;
--note that one of the gt,eq,lt inputs must be tied high
ARCHITECTURE algorithmic OF byte_comparator IS
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Copyright Joanne DeGroat, ECE, OSU

8. Copyright 2006 - Joanne DeGroat, ECE, OSU
The algorithm
BEGIN
PROCESS (a,b,gt,eq,lt)
VARIABLE igt,ieq,ilt : bit_vector (0 to 8);
igt(0) := gt; --connect to external inputs
ieq(0) := eq;
ilt(0) := lt;
FOR i in 0 to 7 loop
igt(i+1) := a (i)AND NOT b(i) OR a(i) AND igt(i)
OR NOT b(i) AND igt(i);
ieq(i+1):=ieq(i) AND (NOT a(i) AND NOT b(i) OR a(i) AND b(i));
ilt(i+1) :=NOT a(i) AND b(i) OR ilt(i) AND NOT a(i)
OR ilt(i) AND b(i);
END LOOP;
a_gt_b <= igt(8); a_eq_b <= ieq(8); a_lt_b <= ilt(8);
END PROCESS;
END byte_comparator;
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Copyright Joanne DeGroat, ECE, OSU

9. Iteration across the slices
For I in 0 to 7 loop
begin
-- do the p operation
-- do the k operation
-- carry out the carry chain unit operations
-- do an r operation
-- will have inputs of a(i),b(i),icin, p,k,r to each slice
-- produce sum(i) and icout
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Copyright Joanne DeGroat, ECE, OSU

10. Copyright 2006 - Joanne DeGroat, ECE, OSU
Internal Connections
Before a signal was used to connect the output of the P unit and the K unit to the carry chain and R unit.
Now time will not advance while in the processes iterations.
What to USE??????
How about a variable
What effect does using a variable have?
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11. Copyright 2006 - Joanne DeGroat, ECE, OSU
The test file
Be sure to properly configure your design into the testbench.
We will start looking at previous steps results.
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Copyright Joanne DeGroat, ECE, OSU