1. ECE 551: Digital System Design & Synthesis
Lecture Set 8
8.1: Miscellaneous Synthesis
8.2: Sequential Synthesis
(In separate file)
03/23/03

2. Overview Synthesis of “x” and “z” Use of Don’t Cares
ECE Digital System Design & Synthesis Lecture Synthesis of Language Constructs
Overview
Synthesis of “x” and “z”
Use of Don’t Cares
Unintentional Latch Inference
Assignments
Continuous assignments
Procedural assignments
Event Controls
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3. Overview (continued) Multi-cycle operations Loops
Static loops
Without internal timing controls
With internal timing controls
Non-static loops
Unnecessary Calculations in for Loops
Disable
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4. Synthesis of “x” and “z” - 1
Only allowable uses of x are in situations that will not result in a x, since x cannot exist in hardware:
in casex
in casez
in defaults of conditionals such as if, case, ?
Only allowable use of z:
Constructs implying a 3-state output
Examples - 3-state structures
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5. Synthesis of “x” and “z” - 2
Example 1:
assign bus_line = (en) ? ckt_out: 32’bz;
Example 2 (Bidirectional)
assign bus_line = (out_en_0) ? data_in: 32’bz; // from 3-state driver at 0 on bus
assign bus_line = (out_en_1) ? data_out : 32’bz; // from 3-state driver at 1 on bus
/* bus_driver serves as input at both points on the bus. Additional three state drivers and input points can be added */
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6. Use of Don’t Cares “x” assigned to wire or reg by UDP
“x” assigned as default in a conditional, case, or casex.
“x, ?, or z” within case item expression in casex
Not actually output don’t cares!
Values for which input comparison to be ignored
Same result could be achieved after logic optimization without use, but description more verbose.
“z, ?” within case item expression in casez
Same conditions as listed above except does not apply to “x”
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7. Unintentional Latch Inference - Avoidance - 1
Avoid structural feedback in continuous assignments and in level triggered behaviors (e.g., combinational always).
Avoid incomplete sensitivity lists for level-triggered behaviors (e. g., combinational always)
See Example 6.16, p. 260 in text
For if, set default values for every LHS by using statements beforehand or specify values for every LHS for each branch.
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8. Unintentional Latch Inference - Avoidance - 2
For case,
set default values for every LHS beforehand or use default in case for every LHS, or
if you know for sure some cases do not occur use compiler directive // synopsys full case
For warning, set hdlin_check_no_latch to true
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9. Assignments Procedural (=) Continuous (assign)
No structural feedback allowed
Procedural (=)
Overridden or ignored in face of procedural continuous assignment
Combined with an assign - procedural continuous assignment - also deassign
force - release NOT supported
Synthesis tool performs expression substitution to get outcome of sequence of procedural (blocking) assignments
LHS variable of statement does not appear on right hand side of assignment operator after expression substitution in non-synchronous assignments (structural loop!)
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10. Event Controls - 1
For combinational model, if some “input” variable missing from event control expression and from procedural continuous assignment, latch implied
If edge qualifier, synchronous
Otherwise, latch or combinational
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11. Event Controls - 2 If synchronous
Given expression synchronous with single edge of single clock
Different behaviors may use different clocks and edges
The Least Common Multiples of the clock periods should not be too large
Other variables are asynchronous control signals and must have edge qualifiers
No given signal may be qualified by both posedge and negedge for a given behavior
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12. Event Controls - 3
A statement associated with event control should be conditional branch (if …, ?…:, case)
Separate into synchronous and asynchronous parts with only one synchronous branch
A branch not dependent upon a signal in the event control expression is assumed synchronous
Synchronous branch must be last in the associated statements
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13. Event Controls - 4 Example:
X or posedge y or posedge z)
begin
if (X)
A <= 0;
else if (Y)
A <= 1;
/*if z is optional here; assumed synchronous, so
else // if (z)
A <= B | C;
...
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14. Multicycle Operations - 1
A multi-cycle operation requires more than one clock cycle to complete
Example: Slow Combinational Multiple - 2 Clock Cycles A B + * C D
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15. Multicycle Operations - 2
Author claims must be distributed over two clock cycles which, in effect, pipelines the operation
Alternatively, use load control (enable):
clock)
begin
load <= ~ load;
C <= A + B;
if (load)
D <= A * B;
In this case, A and B must be held for two clock cycles
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16. Loops
A loop is static (data-independent) if the number of iterations can be determined by the compiler => the number of iterations is fixed
Loop Types
Static without internal timing control
Combinational logic
Static with internal timing control
Sequential logic
Non-static without internal timing control
Not synthesizable
Non-static with internal timing control
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17. Static Loops without Internal Timing Controls
Combinational logic results from “loop unrolling”
Example
begin
for (I = 0; I < 4; I = I + 1)
and[0] = 1;
and[I + 1] = and[I] & a[I];
end
For registered outputs, replace a with posedge clk
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18. Static Loops with Internal Timing Controls
If a static loop contains an internal edge-sensitive event control expression, then activity distributed over multiple cycles of the clock
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19. Non-Static Loops without Internal Timing Controls
The number of iterations in the loop is determined by a variable modified within the loop.
Can be simulated, but not synthesized!
Essentially an iterative combinational circuit of data dependent size!
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20. Non-Static Loops with Internal Timing Controls
The number of iterations is determined by a variable modified within the loop
Due to internal timing control, distributed over multiple cycles with number of cycles determined by variable modified within the loop
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21. Unnecessary Calculations in for Loops
Expressions that are fixed in a for loop are replicated due to “loop unrolling.”
Solution: Move fixed (unchanging) expressions outside of all loops.
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22. FSM Replacement for Loops
Not all loop structures supported by vendors
Can always implement a loop using an FSM even if vendor-support not available directly for construct
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23. Disable External disable infers sequential logic
Race condition possible between function and external disable
Internal disable
If task invoked concurrently from different behaviors, may be disable externally
Synthesis disables only first instance of task
Simulator disables all instances
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