1. How Thin is the Ice? How Variability and Yield Drive Physical Design.
Sani R. Nassif
IBM Austin Research Laboratory

2. Motivation
Modern manufacturing facilities cost »$2B and demand rapid return on investment.
Market windows for leading edge products are less than 12 months.
These two factors put extreme pressure on design teams to produce working high-yield 1st Silicon.
What are the factors that prevent rapid yield learning?

3. Yield… Circuits fail because of:
Catastrophic and random defects which cause structural changes in the net-list (shorts or opens).
Parametric and systematic shifts in electrical behavior of devices and wires reducing operating margins and ultimately performance.
Process-induced variability is increasing as we delve into EDSM (Ever Deeper Sub Micron?).
Systematic (circuit/design limited) yield loss is rapidly becoming as important as defect-limited yield.

4. The Design For Manufacturability Tradition
Academics
Manufacturing
Practitioners
Information Bottleneck
Design
EDA

5. Problems with DFM
Inadequate information flow between design and manufacturing activities.
Example from IBM:
Chip description is 3” thick.
Technology description (manual) is ½” thick.
Limited facilities in design tools for the representation of the process.
Complicated physical phenomena are abstracted into RULES which are then checked for compliance without a clear metric for improvement.
Wisdom

6. Outline Variability Analysis of variability. Variability forecasts.
Sources.
Impacts.
Models.
Analysis of variability.
Variability forecasts.

7. Variability Sources Physical: Parametric and Catastrophic.
Changes in characteristics of devices and wires.
Caused by the IC manufacturing process and wear-out.
Time scale of 109 sec (years).
Environmental:
Parametric.
Changes in VDD, Temperature, local coupling.
Caused by the specifics of the design implementation.
Time scale of 10-6 to 10-9 sec (clock tick).

8. Variability and PD Physical: Parametric: Catastrophic:
Traditionally handled with worst-case corner files.
Within-chip variability co-generated with the process.
(depends on detailed layout of the design!)
Catastrophic:
Strong function of detailed layout!
Environmental (Parametric only):
Wire/Image planning determines VDD variability.
Floor-plan determines T variability.
Detailed routing determines coupling variability.

9. Variability vs. Uncertainty
Variability: quantitative relationship to source (model) is known.
Designer has option to null out impact.
Uncertainty: magnitude determined by characterization.
Can only be treated by worst-case analysis.
Lack of modeling resources can transform variability to uncertainty.
Example: nearest neighbor noise coupling.
Wisdom

10. Sources of Uncertainty
Design uncertainty:
Portions not yet defined.
Changes in specification.
Modeling uncertainty:
Lack of detail in models.
Pessimism/conservatism (rules!).
Processing uncertainty:
Manufacturing noise (e.g. LEFF).
Changes as technology matures.
Accuracy needed relatively late in the design cycle.
Uncertainty
Accurate process
noise needed
Design
Design
complete
Model
Process
Time

11. Outline Variability Analysis of variability. Variability forecasts.
Sources.
Impacts.
Models.
Analysis of variability.
Variability forecasts.

12. Impact of Variability Timing in a synchronous digital circuit:
Single distributed clock.
Logic bounded by clocked latches.
Correctness: signals obey certain timing inequalities.
Performance: clock period.
Robustness: timing margin in the presence of variability.
Launch
Capture
Path 1 LL LC
Logic
Path 2 LL LC
Logic
Clock A
Clock B
Clock

13. Variability and Timing
TA + T1 £ TB + TPeriod
TA + T1 ³ TB
TA + T2 £ TB + TPeriod
Launch T1
Capture
Path 1 LL LC
Logic
Performance T2
Path 2 LL LC
TB + TPeriod
delay
Logic
wire
margin
TA + T1
T1 device dominated TA
Clock A
Clock B TA TB
Relative wire delay
Clock

14. Timing Correctness TA + T2 £ TB + TPeriod Failure TA + T2 TB + TPeriod
Launch T1
Capture
Path 1
Failure LL LC
TA + T2
Logic
delay
TB + TPeriod T2
margin
Path 2 LL LC
T2 device+wire
Logic TA
wire
Relative wire delay
Increased variability ® reduced margin ® increased period ® reduced performance.
Wisdom
Clock A
Clock B TA TB
Clock

15. Outline Variability Analysis of variability. Variability forecasts.
Sources.
Impacts.
Models.
Analysis of variability.
Variability forecasts.

16. A Typical Scenario: Parametric
Fab E-Test data
Statistical
Modeling
Process
Limits
Design Corners
Design
Simulation
Performance
Estimates
Deterministic
Modeling
Operating
Conditions
Yield
Estimate

18. A Typical Scenario: Catastrophic
Fab Defect data
Design
Critical Area
Analysis
Failure
Estimates
Yield
Estimate

19. What is a Defect Anyway?
Wire 1
Short
Wire 2

20. Within-Die Variations?
Environmental components:
VDD & Temperature variations are natural byproducts of power distribution analysis.
Power analysis is going to be unavoidable in EDSM.
Easy but BIG analysis problem.

21. Spatial Parametric Variability
Lot, wafer & die levels.
Lot Level.
Not of interest to designer.
Wafer Level.
Smooth variations across wafer.
Locally (within die) linear position dependence.
Chip Level.
Layout dependent .
Die 2
Die 1
wafer
Parameter
Position
Die 1
Die 2

22. Layout-Dependent Variations
Poly line-width (LEFF) variation comes from:
Mask variations
Exposure variations
Etch variations
Wire-width variations have similar sources.
Layout
Mask
Resist
Poly
Silicon

23. Modeling of LEFF Variations
EDSM processes will use optical pattern correction (OPC) to improve image quality at the poly-silicon level.
Infrastructure required to perform OPC is the same as that required to predict 1st order interaction between layout and DL!
Go for it…
PD should get involved with the physics and SPICE types to make this a reality.

24. Modeling of Wire Variations
Horizontal variations are similar to those of LEFF
Different processing steps  no correlations with LEFF. .
Vertical variations are caused by chemical-mechanical planarization (CMP) process.
polishes
faster C1 C2

25. Variations: Summary
Traditional view: process parametric variations are imposed upon a design.
Everything is random.
Worst-Case corners constitute a complete description of the process.
DSM view: process variations interact with the design causing within-die variations.
Physical (line width, ILD, etc...).
Environmental (temperature, supply).
Comparable in magnitude to die-to-die variations.
Variability comes from non-uniformity!
Wisdom

26. Outline Variability. Analysis of variability Variability forecasts.
Critical Area Analysis.
Statistical Analysis (Die to Die).
Statistical Analysis (Within Die).
Variability forecasts.

27. Critical Area Analysis
Now a staple for catastrophic yield analysis.
Example of transformation from rule-based analysis to goodness-metric-based analysis.
Active current research to improve performance and allow automated optimization.
Defect
Center

28. Some “DUH” Solutions…
Wire
Spreading
Uniformity  Decreases Critical Area AND Variability!

29. Outline Variability. Analysis of variability Variability forecasts.
Critical Area Analysis.
Statistical Analysis (Die to Die).
Statistical Analysis (Within Die).
Variability forecasts.

30. Performance Estimation
Basic assumptions:
Performance measured by simulation.
Technology represented by model parameters.
Parameters have statistical distributions.
Nominal performance estimation:
Simulator
Design
Description
Operating
Environment
Model
Parameters
Performance
Estimate

31. Statistical Performance Estimation
Model Inaccuracy
Process
Variations
Vdd, T
Noise
Model
Parameters
Simulator
Performance
Distribution
Design
Description PD
Operating
Environment
Model inaccuracy need not be correlated with, and cannot be distinguished from process variations.
Wisdom

32. Classical Statistical Analysis
Given:
A design specification.
Target performance, z.
Determine:
The expected ns spread of z.
Worst or extreme case analysis.
The distribution of z.
Yield estimation.
How to change design to improve yield.
Yield maximization.

33. Outline Variability. Analysis of variability Variability forecasts.
Critical Area Analysis.
Statistical Analysis (Die to Die).
Statistical Analysis (Within Die).
Variability forecasts.

34. Analysis of Within-Chip Variability
After physical design (layout):
Apply models for spatial variations.
P(x,y) = W(w,x,y) + N(0,s2)
w are the parameters of the spatial variation model.
Example: wire capacitance as a function of inter-dielectric thickness variations due to Chemical-Mechanical Polishing density dependence.
Perform worst case analysis with respect to w.
Before physical design (or... model not available):
Spatial dependence not available.
P(x,y) = N(m,s2)
Max/Minimize performance subject to maintaining statistics.
Wisdom

35. Example
Skew in an H-Tree clock distribution network.
Skew B

36. Why Skew? TA + T1 £ TB + TPeriod TA + T1 ³ TB TA + T2 £ TB + Tperiod
Skew is TA - TB
Launch T1
Capture
Path 1 LL LC
Logic T2
Path 2 LL LC
Logic
wire
Clock Period
Useful Work
Skew
Clock A
Clock B TA TB T1
TA - TB
Clock

37. Example: LEFF Variations
Impact of Poly-Silicon mask, lithography and etch at the chip level.
Each buffer (total of 65) has a unique value of LEFF.
Values of LEFF obey a normal distribution.
max Skew(LEFF)
s.t. mean(LEFF) = m
and stdv(LEFF) = s B
Skew

38. Results for LEFF Dark: short. Skew insensitive to top half of H-Tree.
Sensitivity increases closer to the leaves of the H-Tree.
Non-statistical worst case is 23% more pessimistic.
change LEFF to +3s or -3s depending on sensitivity.
Better analysis got us 23% closer to the edge!
Wisdom

39. Another View of LEFF Worst case for wafer- level variations.
LEFF modeled as a linear function of position.
Much smaller skew.
Chip

40. Results for Wire Variations
Each wire segment was one variable (63 total).
Dark: wide.
Skew most sensitive to wires at the root of the tree hierarchy.
Non-statistical worst case is 18% more pessimistic.

41. Outline
Variability.
Analysis for variability
Variability forecasts.

42. Caveats Digital/ASIC-centric view.
Many phenomena of interest to analog designers have yet to impact high performance digital design.
Forecasting of technology-related parameter variability is inaccurate.
Rely on NTRS and ITRS documents + insight from IBM technologies.
Inspired by W. Maly.
Sensitivity to variability is a strong function of circuit family and design style.
Conclusions here limited to static CMOS buffer delays.

43. Canonical Circuit
Needed to assess impact of variability over technology generations.
Inverter/buffer followed by a wire.
Length of wire determined to minimize delay.
If the wire were longer, a buffer would be inserted. RB CB CW RW tB

44. The NTRS Technologies

45. Parameter Variations (Total)%
Leff
W, H, T, r
VDD, TOX, VT

46. Wire vs. Device Variability
Percentage of variability
due to device variations.
Uniform Shrink:
Constant W/L,
wire length a Leff
Smart Shrink:
Constant W/L,
wire length=LMAX
Device shrink:
Constant W,
wire length=LMAX

47. Conclusions
Variability plays an important and increasingly dominant part in high performance design.
Existing DA tools and models of technology are insufficient to handle DSM variability.
Tools need to migrate from rule checking to “goodness metric” estimation and improvement.
Research is needed in models and analysis.
Better models of variations can lead to tightened margins.
Current analysis methodologies are SPICE-based and severely limited in capacity.
Yield and $ are tightly coupled. Mistakes are costly.
Analysis for now… automatic optimization later. 21