1. EE 201C Modeling of VLSI Circuits and Systems Chapter 1 Introduction
Instructor: Lei He

2. Instructor Info
Phone:
Office: Boelter Hall 6731D
Office hours:
Tus 2-3pm
Thur 4-5pm
or by appointment
The best way to reach me:
with EE201 in subject line
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

3. VLSI Design and Verification Cycle
System Specification
Functional Design and Verification
X=(AB*CD)+(A+D)+(A(B+C))
Y=(A(B+C))+AC+D+A(BC+D))
Logic Design and Verification
Circuit Design and Verification
Verification techniques
Formal verification
Logic/circuit simulation
Functional and logic emulation

4. VLSI Design and Verification Cycle (cont.)
Physical Design and Verification
Fabrication and Testing
Packaging
Layout verification
LVS, DRC, ERC
Timing, SI, PI, DFM (applied to circuit design as well)
Modeling and simulation is a core component for design and verification considering timing/SI/PI/DFM

5. CAD Courses at UCLA EE dept. CS dept.
EE201A Fundamental to CAD (Spring)
Basics to all aspects of CAD
More on combinatorial optimization
EE201C this course
Modeling and simulation of timing, signal/power integrity, power and thermal, and manufacturability
Co-development of modeling and optimization
CS dept.
CS258F Physical design of VLSI circuits
CS258G Logic synthesis of VLSI circuits
CS259 High Level Synthesis (taught by Miodrag)
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

6. EE201C Prerequisites Official prerequisite
EE116B VLSI System Design
But mainly self-contained
Knowledge to help you appreciate more
CS180 Introduction to algorithms
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

7. 201C Course Outline and Schedule
Power and thermal modeling (2 weeks)
Power and thermal modeling in FPGA and microprocessor
Report and presentation on ITRS roadmap
Interconnect modeling and optimization (4 weeks)
Interconnect extraction
Model order reduction
Signal integrity and power integrity
Project 1: (around 5th week)
Design for manufacturability (3 weeks)
CMOS device modeling and process variation modeling
Stochastic static timing analysis
Final project by end of the quarter (or one week afterwards)

8. ITRS Assignment Read ITRS roadmap newest edition
ITRS: International technology roadmap for semiconductor
Executive summary + one chapter related to your research interest
Write a four-page summary to discuss the selected chapter
Use the style of ACM conference papers
Prepare five-page slides for short-presentation
Report due by midnight of Sunday, Oct 7th
All reports in style of ACM conferences
Submitted by in pdf files

9. Projects Project 1: Matlab coding of PRIMA
model order reduction method
Majority of program is given
Required for every one
Final project (one of the following two):
One-person survey and critic of selected topic (at most 35%)
Individual programming project for a team of 2 to 3 persons
Any topic agreed by instructor
Up to 30 minute presentation during the finals week, like a conference talk
Up to 12 page report
Use ACM style

10. More on Final Projects
Final project could be supervised by Prof. Puneet Gupta
With expertise on design for manufacturability, and manufacture for design
He will give one or two lectures in this class and is looking for research assistants

11. References for this Course
Selected papers leading journals and conferences
Tan and He, “Advanced Model Order Reduction Techniques for VLSI Designs”, Cambridge University Press, pp 1-217, 2006
H. Bakoglu, Circuits, Interconnects, and Packaging for VLSI, Addison Wesley
Web site of previous year
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

12. Related VLSI CAD Conferences
ACM IEEE Design Automation Conference (DAC)
(San Diego, Young student program)
International Conference on Computer Aided Design(ICCAD)
Design, Automation and Test in Europe (DATE)
Asia and South Pacific Design Automation Conference (ASP-DAC)
International symposium on physical design (ISPD)
International symposium on low power electronics and design
International symposium on field programmable gate array
IEEE International Symposium on Circuits and Systems (ISCAS)

13. Related VLSI CAD Journals
IEEE Transactions on CAD of Circuits and systems (TCAD)
IEEE Trans. on VLSI Systems (TVLSI)
ACM Trans. on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Circuits and Systems (TCAS)
IEEE Trans. on Computer

14. Grading Policy Matlab Project 1 20% Course presentation 30%
ITRS report and presentation %
Other presentations %
Final project 50%
A  score > 85
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

15. Course Presentation (20%)
2~3 student a team, one or two talks per team
Each talk surveys one topic (topics specified by me on a continual basis)
One on classic problem (may provide slides)
One on frontier research (need to prepare slides)
Prepare slides for a 45 minute presentation
slides prepared jointly
either all students share the presentation or I will select the speaker randomly at the presentation time
For either talk, prepare a web site that should contain a report based on your survey, a bibliography, and links to resources and of course your slides

16. Who should take this course
It is another course
Discuss wide scope of knowledge
But research (presentation + project) on your own focus
For students who are motivated to
Learn SI, power/thermal, DFM for advanced designs
Learn algorithm basics without taking CS280
Understand CAD better
Become a CAD professional
I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the
LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.