1. SAT-based Methods: Logic Synthesis and Technology Mapping
Alan Mishchenko Robert Brayton
Department of EECS
UC Berkeley

2. Overview Understanding a SAT solver SAT-based technology mapping
Structural (LUTs and standard cells)
Functional (standard cells)
Functional (LUTs)
SAT vs. other computation engines
Experimental results 2

3. Boolean Satisfiability
Given a formula representing Boolean function (x), satisfiability problem is to prove that (x)  0, or to find a counter-example x’ such that (x’)  1
In many applications the formula is in CNF
CNF (Conjunctive Normal Form) is the product of sums, for example (x1, x2) = (x1 + x2)(!x1 + x2)
If CNF was canonical (like BDD), it would be trivial to solve the satisfiablity problem
But CNF is not canonical; CNF can be very redundant, so that a large formula is, in fact, equivalent to 0.

4. Example (Deriving CNF)ab
(a + b + c)
(a + b + c’)
(a’ + b + c’)
(a + c + d)
(a’ + c + d)
(a’ + c + d’)
(b’ + c’ + d’)
(b’ + c’ + d) cd 00 01 11 10 1
Cube: bcd’
Clause: b’ + c’ + d

5. Boolean Satisfiability
Netlist
Answer: “SAT” or “UNSAT”
CNF
SAT solver
CNF generator
CNF
Design constraints
If SAT, a counter-example
If UNSAT, a proof
(both counter-examples and proofs are very useful in practice)
User cost functions
Miter
Typical application: Equivalence Checking
Build circuit Miter = (Specification != Implementation)
Convert Miter into CNF and run SAT solver
- If UNSAT, equivalence checking succeeds
- If SAT, use the counter-example to debug the design
Output
Spec
Impl
Inputs

6. Incremental SAT Solver
Initial CNF
Round 1:
SAT solver
Initial assumptions
Additional CNF
Round 2:
SAT solver
New assumptions
Additional CNF
Round 3:
SAT solver
New assumptions
(assumptions are CNF clauses used only in the current round – they are handled differently from the rest)
Typical application: Bounded Model Checking
Load init and the first time frame
until (SAT solver returns “UNSAT”) {
add clauses for the next time frame } P P P T1 T2 T3 …
Init

7. A Note on Counter-Examples
Counter-example (CEX) is an assignment of SAT variables that makes all CNF clauses satisfied
For this, we check whether ONSET(x) = 1 is true
CNF-based SAT solvers (in particular, MiniSAT), always return a complete assignment of variables (a minterm)
In practice incomplete assignments are often preferred
For this, we need to expand an assignment minterm by dropping (expanding) some of its literals, making it a cube
To expand an assignment, we use the off-set (similar to “expanding a cube against the off-set” in ESPRESSO)
We solve SAT instance: ONSET_minterm(x) & OFFSET(x) = 0
A proof of unsatisfiability tells us what literals to expand

8. A Note on Proofs
Proof of unsatisfiability (POU), is a sequence of resolution steps, which derives empty clause (contradiction) from the original clauses
POU can be used to compute an UNSAT core (a subset of original clauses, which make the problem UNSAT)
Computing the full POU/core is often not necessary
A practical alternative computes an abstraction of the core in the form of a subset of assumptions needed for the problem to be UNSAT
This is achieved by a special API of the SAT solver (analyze_final)
This API is very fast because it simply performs conflict analysis one more time, on the top level
This API is very practical because it allows UNSAT runs to be as useful as SAT ones, without recording and traversing the complete POU

9. SAT-based Structural Mapping
Input the original mapped circuit and the library
Iterate over small multi-output cones (10-20 gates each) in some order
Convert the cone into an AIG
Compute cuts and matches for each AIG node using the library
Describe the set of all structural gate covers of the cone as a CNF
Introduce one SAT variable for each node polarity and for each cut
If a node is used in the mapping, it implies that one of its cuts is used
If a cut is used, it implies that the root and the leaf nodes are used
The output nodes should be used in the mapping
Cardinality constraint limits the gate count
Solve incremental SAT
Incrementally reduce solution cardinality if needed
Timing constraints are handled as a SAT solver callback
If there is an improvement, replace original mapping of the cone by the new one
Output an improved circuit

10. CNF / Mapping Terminology
CNF is composed of variables, literals, and clauses
Each variable represents some aspect of the problem
Each literal is a variable in positive or negative polarity
Each clause is a disjunction of literals
CNF is a conjunction of clauses
Mapping is a set of gates completely covering the subject graph
Internal nodes of the subject graph can be
Used in the mapping (if mapping includes a gate rooted in this node)
Not used in the mapping (otherwise)
Gate cover represents a valid mapping if
Internal nodes driving the circuit outputs are used in the mapping
For each gate, its inputs are used in the mapping or are primary inputs

11. CNF for Structural Mapping
Disclaimer! This is a simplified formulation of standard-cell mapping
assumes one variable per node (rather than two variables for each polarity)
CNF variables
one variable (ni) for each node
ni is 1, iff node i is used in the mapping
one variable (cik) for each match (cut + gate) of the node
cik is 1, iff match k is used to map node I
CNF clauses
ni  k (cik) (If a node is used, one of its matches is used)
cik  f (nf) (If a match is used, all cut fanins are used)
o (no) (The nodes driving the outputs are used in the mapping)
i ni ≤ Limit (The gate count does not exceed the known mapping)

12. Handling of Timing Constraints
Timing constraints can be simplified (discretized) and turned into CNF
However, this leads to an increase in CNF size and a slowdown in solving
A better way to handle such constraints, is to use a dedicated constraint propagation engine (in this case, a timer)
SAT solver and the timing engine interact similar to how SMT solver is built around a SAT solver and one or more domain solvers
SAT solver leads the constraint propagation and passes partial assignments to the domain solvers, which propagate them on the domain constraints and return learned clauses to SAT solver
In the context of a technology mapping, it means that SAT solver finds valid structural mappings, repeatedly evaluated by the timer
If the timer finds that the mapping meets the timing, a solution is found
Otherwise, the timer returns the critical path, which is interpreted as a blocking clause by the SAT solver
The SAT solver continues to explore the search space until it either
Finds a mapping that satisfying the timing
Returns UNSAT after exploring all valid mappings
Runs out of resources (runtime, memory, etc)

13. SAT-based Functional Mapping
Input the original mapped circuit and the library
Preprocess the library by combining gates into “super-gates” characterized by area, delay, and Boolean function (as a truth table)
Iterate over gates in some order
Compute a local window centered in this gate
Construct CNF of the Boolean relation relating the gate output and the outputs of other gates in the window
Use the SAT solver to perform recursive cofactoring of the Boolean relation, resulting in several alternative implementations of the gate
Express each implementation as a super-gate in the precomputated library
Evaluate each implementation in terms of area/delay and find the best one
If there is an improvement, replace original gate by the new one
Output an improved circuit

14. Local Window of a Node Definition A window includes
A window for a node in the network is the context, in which its functionality is considered
A window includes
k levels of the TFI
m levels of the TFO
all re-convergent paths captured in this scope
Window POs
Window PIs
k = 3
m = 3

15. Constructing Boolean Relation of the Node and Candidate Divisors1
Construction steps:
Collect candidate divisors di of node n
Divisors are not in the TFO of n
Their support is a subset of that of node n
Duplicate the window of node n
Use the same output variables
Add inverter for node n in one copy
Create comparator for the outputs
Set the comparator to 1
This is the care set of node n
Convert all gates to CNF … d2 n n d1
How the relation is used:
Function n = F(d1, d2, …) belongs to the relation iff n can be implemented as a gate with function F in terms of divisors d1, d2, …
SAT solver is used to recursively cofactor the relation using different variable orders, resulting in several qualifying functions F X

16. SAT-based Relation Solving
Given Boolean relation in CNF, find contained Boolean function(s)
Pseudo-code
function SolveBR_rec( ordered set of divisors D, assigned divisors A, cnf C ) {
if ( F=1 is UNSAT under assumptions in A ) return 0;
if ( F=0 is UNSAT under assumptions in A ) return 1;
if ( F=di or F=!di for a divisor di in D under assumptions in A ) return di or !di;
d = the topmost variable in D;
return d ? SolveBR_rec( D/d, A  d=1, C ) : SolveBR_rec( D/d, A  d=0, C ); }
functions SolveBR( number of functions N, set of divisors D, cnf C ) {
result = ;
for ( i = 0; i < N; i++ ) {
find a new ordering of divisors in D;
result = result  SolveBR_rec( D, , C );
return result;

17. Experimental Results
Experimenting only with SAT-based functional mapper
The results explore scalability of the mapper
Using 10 large combinational logic cones
A typical run
abc 01> r ex02.aig; amap; ps; mfs3 -aev -I 4 -O 2; ps; time; echo
ex : i/o =25237/ lat = nd = edge = area = delay = lev = 13
Library processing: Var = 6. Cell = 71. Fun = Obj = Ave = Skip = 0. Rem = 0. Time = sec
Remapping parameters: TFO = 2. TFI = 4. FanMax = 10. MffcMin = 1. MffcMax = 3. DecMax = 1. 0-cost = no. Effort = yes. Sim = no.
Node = Try = Change = Const0 = 0. Const1 = 0. Buf = 44. Inv = Gate = AndOr = 0. Effort = 962.
MaxDiv = 111. MaxWin = AveDiv = 8. AveWin = Calls = (Sat = Unsat = ) Over = 0. T/O = 0.
Lib = sec ( %)
Win = sec ( %)
Cnf = sec ( %)
Sat = sec ( %)
Sat = sec ( %)
Unsat = sec ( %)
Eval = sec ( %)
Timing = sec ( %)
Other = sec ( %)
ALL = sec ( %)
Cone sizes: 1= =5 3=164 4=34 5=861 6=1 Gate sizes: 1= =897
Reduction: Nodes out of ( %) Edges out of ( %)
ex : i/o =25237/ lat = nd = edge = area = delay = lev = 13

18. Experimental Results
Area-only mapping was performed using a unit-area library.
Parameters of mfs3 were selected to match the runtime of amap and &nf.
Each of these commands took about 3 min for all benchmarks listed.

19. SAT-Based Delay Optimization
This is a recent project started a few month ago, currently in the tuning phase
Structural LUT mapping is delay-optimal for a fixed structure of the subject graph (J.Cong et al, FlowMap, 1994)
The goal is to prepocess an AIG given to a tech-mapper to have a new structure that enables mapping with a shorter delay

20. Comparing Delay-Opt Methods

21. Overview of Optimization Framework

22. Delay Prediction Nodes are considered in a topological order
Mapping into K-LUTs is performed for each node (suppose the resulting delay is D)
SAT-based optimization is applied, trying to reduce node’s delay from D to D-1
For this Boolean divisors of the node whose logic levels is D-2 or less are considered
A good set of divisors is computed and used to re-express the node
D 
D-1
D-2
D-3

23. Window Representing Care Set1 … d2 n n d1 X

24. Divisor Selection
Currently, one delay-driven structural cut is considered as a starting set of divisors
The set is minimized using SAT solver by trying to remove one variable at a time
The resulting set is checked for delay-feasibility for a LUT structure (say, “44”)

25. Synthesizing a LUT-structure Implementing Function on a Care Set
Formulated as a QBF problem: px [S(x, p) == F(x)]
To solve QBF, we use two SAT solvers:
One solver represents the care-set of the node in the window
Another solver is used to solve QBF instance incrementally
Main difference with previous work on “QBF-based LUT structure evaluation”, is that we do not encode LUT variable connectivity in CNF
As a result, QBF solving is fast

26. Experimental Results The method is implemented as command &mfsd
It is compared with mapping into LUT structures composed of two 4-input LUTs (called S44)
The two methods are similar
they are used for delay-optimization
they are based on dynamic programming
they use AIG is an underlying data-structure
they generate new delay-oriented cut-points (these are outputs of the bottom LUT feeding into the top LUT)

27. Summary of Results
Considered a suite of 60 industrial designs ranging in size from 1K to 50K 4-LUTs.
Performed 3 runs: (1) S44, (2) &mfsd, (3) S44 + &mfsd.
&mfsd (2) improved delay by 4.0% compared to S44 (1)
S44 + &mfsd (3), improved delay by 5.3%, compared to S44 (1)
The runtimes are reasonable; for the largest examples, &mfsd is 3-5x longer than S44 and takes less than 5 min
Currently, area increase is about 10%; should be less after turning

28. SAT vs. Other Computation Engines
The presented computations can be implemented with any computation engine
SAT, BDDs, SOPs, truth tables, etc
The implementations differ greatly in terms of
Complexity
Resource usage
Quality of results
Scalability
Based on these metrics, SAT-based implementations are rated highly
Relatively easy to implement (using an off-the-shelf solver)
Relatively inexpensive (both memory and runtime requirements are reasonable)
Good quality of result (typically, there is no clear win against other method)
The most scalable among known engines (this is the main advantage!)
The main reason why SAT is more scalable than BDDs
BDDs require construction of a canonical form before they can be used
CNF construction is linear; therefore, SAT can start working on the problem right away
As a result, SAT has more chances to solve a hard instance of an NP-hard problem

29. Conclusion
Introduced the SAT solver as a powerful Boolean computation engine
Reviewed several SAT-based algorithms
Circuit restructuring by ISOP computation
Technology mapping based on two orthogonal approaches
Finding a better gate cover (structural mapping)
Finding a better functional expression (functional mapping)
Discussed the key difference between SAT and BDDs
And why SAT replaced BDDs in most of the application domains

30. Abstract
This presentation focuses on the use of Boolean satisfiability as a computation engine in solving typical problems arising in logic synthesis and technology mapping. In particular, a new SAT-based algorithm is presented to compute canonical irredundant sums-of-products (ISOPs) similar to Minato’s well-known BDD/ZDD-based ISOP computation. In addition, two SAT-based technology mappers are discussed: a functional mapper, which exploits don't-cares of a node in the network, and a structural mapper, which searches the space of all structural covers. Both mappers take a mapped network and improve it based on a user-specified cost function. The mappers are applicable to both standard-cells and lookup tables.