1. Lecture 20
State minimization via row matching

2. FSM minimization
Two simple FSMs for odd parity checking

3. Collapsing states
Can collapse S0 and S2 into one state

4. FSM minimization Row matching Implication chart Easier to do by hand
Misses minimization opportunities
Implication chart
Guaranteed to find the most reduced FSM
More complicated algorithm (but still relatively easy to write a program to do it)

5. Simple problem
Design a Mealy machine with a single bit input and a single bit output. The machine should output a 0, except once every four cycles, if the previous four inputs matched one of two patterns (0110, 1010)
Example input/output trace: in: … out: …

6. … and a simple solution

7. Find matching rows Next State Output Input Sequence Present State X=0
Reset S0 S1 S2 S3 S4 1 S5 S6 00 S7 S8 01 S9
S10 10
S11
S12 11
S13
S14
000
001
010
011
100
101
110
111

8. Find matching rows Next State Output Input Sequence Present State X=0
Reset S0 S1 S2 S3 S4 1 S5 S6 00 S7 S8 01 S9
S10 10
S11
S12 11
S13
S14
000
001
010
011
100
101
110
111

9. Merge matching rows Next State Output Input Sequence Present State X=0
Reset S0 S1 S2 S3 S4 1 S5 S6 00 S7 S8 01 S9
S10’ 10
S11 11
S13
S14
000
001
010
011 or 101
100
110
111

10. Merge until no more matches
Next State
Output
Input Sequence
Present State
X=0
X=1
Reset S0 S1 S2 S3 S4 1 S5 S6 00
S7’ 01
S10’ 10 11
Not (011 or 101)
011 or 101

11. Final state transition table
Next State
Output
Input Sequence
Present State
X=0
X=1
Reset S0 S1 S2
S3’
S4’ 1
00 or 11
S7’
01 or 10
S10’
Not (011 or 101)
011 or 101

12. Final FSM