1. Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/
EE5342 – Semiconductor Device Modeling and Characterization Lecture 20 March 31, 2010
Professor Ronald L. Carter

2. Schedule Change Classes WILL be held on
4/5/10
4/7/10
Dr. Russell will be filling in
The previously scheduled make-up classes will be cancelled
4/16/10 (Friday)
4/23/10 (Friday)
Project 2 Test changed to W 4/28/10
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3. Inversion for p-Si Vgate>VTh>VFB
Vgate> VFB
EOx,x> 0
e- e- e- e- e-
Depl Reg
Acceptors
Vsub = 0
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4. Inversion for p-Si Vgate>VTh>VFB
Fig 10.5*
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5. Approximation concept “Onset of Strong Inv”
OSI = Onset of Strong Inversion occurs when ns = Na = ppo and VG = VTh
Assume ns = 0 for VG < VTh
Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh
Cd,min = eSi/xd,max for VG > VTh
Assume ns > 0 for VG > VTh
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6. MOS Bands at OSI p-substr = n-channel
Fig 10.9*
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7. Equivalent circuit above OSI
Depl depth given by the maximum depl = xd,max = [2eSi|2fp|/(qNa)]1/2
Depl cap, C’d,min = eSi/xd,max
Oxide cap, C’Ox = eOx/xOx
Net C is the series comb
C’Ox
C’d,min
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8. MOS surface states** p- substr = n-channel

9. n-substr accumulation (p-channel)
Fig 10.7a*
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10. n-substrate depletion (p-channel)
Fig 10.7b*
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11. n-substrate inversion (p-channel)
Fig 10.7*
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12. Values for gate work function, fm

13. Values for fms with metal gate

14. Values for fms with silicon gate

15. Typical fms values
Fig 10.15*
fms
(V)
NB (cm-3)
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16. Flat band with oxide charge (approx. scale)
SiO2
p-Si
+<--Vox-->-
q(Vox)
Ec,Ox
q(ffp-cox)
q(fm-cox) Ex
Eg,ox~8eV
EFm Ec
EFi
EFp
q(VFB) Ev
VFB= VG-VB, when Si bands are flat Ev
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17. Flat-band parameters for n-channel (p-subst)

18. Flat-band parameters for p-channel (n-subst)

19. Inversion for p-Si Vgate>VTh>VFB
Vgate> VFB
EOx,x> 0
e- e- e- e- e-
Depl Reg
Acceptors
Vsub = 0
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20. Approximation concept “Onset of Strong Inv”
OSI = Onset of Strong Inversion occurs when ns = Na = ppo and VG = VTh
Assume ns = 0 for VG < VTh
Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh
Cd,min = eSi/xd,max for VG > VTh
Assume ns > 0 for VG > VTh
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21. MOS Bands at OSI p-substr = n-channel
Fig 10.9*
2q|fp|
qfp
xd,max
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22. Computing the D.R. W and Q at O.S.I.Ex
Emax x
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23. Calculation of the threshold cond, VT

24. Equations for VT calculation

25. n-channel VT for VC = VB = 0
Fig 10.20*
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26. Fully biased n-MOS capacitorVG
Channel if VG > VT VS VD
EOx,x> 0 n+
e- e- e- e- e- e- n+
p-substrate
Vsub=VB
Depl Reg
Acceptors y
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27. Fully biased MOS capacitor in inversion
Channel
VG>VT
VS=VC
VD=VC
EOx,x> 0 n+
e- e- e- e- e- e- n+
p-substrate
Vsub=VB
Depl Reg
Acceptors y
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28. Flat band with oxide charge (approx. scale)
SiO2
p-Si
+<--Vox-->-
q(Vox)
Ec,Ox
q(ffp-cox)
q(fm-cox) Ex
Eg,ox~8eV
EFm Ec
EFi
EFp
q(VFB) Ev
VFB= VG-VB, when Si bands are flat Ev
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29. Flat-band parameters for n-channel (p-subst)

30. MOS energy bands at Si surface for n-channel
Fig 8.10**
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31. Computing the D.R. W and Q at O.S.I.Ex
Emax x
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32. Q’d,max and xd,max for biased MOS capacitor
Fig 8.11**
|Q’d,max|/q (cm-2)
xd,max (microns)
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33. Fully biased n- channel VT calc

34. L20 03/31/10

35. Computing the threshold voltage

36. L20 03/31/10

37. n-channel VT for VC = VB = 0
Fig 10.20*
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38. Flat-band parameters for p-channel (n-subst)

39. Fully biased p- channel VT calc

40. p-channel VT for VC = VB = 0
Fig 10.21*
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41. Ion implantation
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42. “Dotted box” approx
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43. L20 03/31/10

44. Mobilities
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45. Differential charges for low and high freq
From Fig 10.27*
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46. Ideal low-freq C-V relationship
Fig 10.25*
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47. Comparison of low and high freq C-V
Fig 10.28*
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48. Effect of Q’ss on the C-V relationship
Fig 10.29*
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49. n-channel enhancement MOSFET in ohmic region
0< VT< VG
Channel
VS = 0
0< VD< VDS,sat
EOx,x> 0 n+
e-e- e- e- e- n+
Depl Reg
p-substrate
Acceptors
VB < 0
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50. Conductance of inverted channel
Q’n = - C’Ox(VGC-VT)
n’s = C’Ox(VGC-VT)/q, (# inv elect/cm2)
The conductivity sn = (n’s/t) q mn
G = sn(Wt/L) = n’s q mn (W/L) = 1/R, so
I = V/R = dV/dR, dR = dL/(n’sqmnW)
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51. Basic I-V relation for MOS channel

52. I-V relation for n-MOS (ohmic reg)ID
non-physical
ID,sat
saturated
VDS,sat
VDS
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53. Universal drain characteristicID
VGS=VT+3V
9ID1
ohmic
saturated, VDS>VGS-VT
VGS=VT+2V
4ID1
VGS=VT+1V
ID1
VDS
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54. Characterizing the n-ch MOSFETVD ID D G S B VT
VGS
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55. Low field ohmic characteristics

56. MOSFET Device Structre Fig. 4-1, M&A*
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57. 4-7a (A&M)
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58. Figure 4-7b (A&M)
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59. Figure 4-8a (A&M)
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60. Figure 4-8b (A&M)
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61. Body effect data
Fig 9.9**
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62. References
* Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997.
**Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986
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