1. Lecture 23

2. DMA Cascading

3. DMA Programming Model DMA has 4 – Channels
Each Channel can be programmed to transfer a block of maximum size of 64k.
For each Channel there is a
Base Register
Count Register
Higher Address Nibble/Byte is placed in Latch B.
The Mode register is conveyed which Channel is to be programmed and for what purpose i.e. Read Cycle, Write Cycle, Memory to memory transfer.
A request to DMA is made to start it’s transfer.

4. Internal Registers No of 16 & 8 bit Internal registers
Total of 27 internal registers in DMA
Register Number Width
Starting Address
Counter
Current Address
Current Counter
Temporary Address
Temporary Counter
Status
Command
Intermediate Memory
Mode
Mask
Request

5. DMA Modes
Block Transfer
Single Transfer
Demand Transfer

7. DMA Status Register

8. DMA Command Register