1. Basics of Embedded Systems IAX0230 Time Interfacing
Assoc. Prof. Dr. Kalle Tammemäe
Prof. Dr.-Ing. Thomas Hollstein
Dr. Uljana Reinsalu

2. Outline Clocking Interrupts Timers / Cyclic interrupts Watchdogs
Cyclic Output: PWM

3. Cortex M4 Clocking Precision internal oscillator (PIOSC):
16 MHz
Main Oscillator (MOSC):
Operates with external chrystal
Low-Frequency Internal Oscillator (LFIOSC):
Used in deep-sleep power saving modes
Hybernation Module clock source
32.768kHz, accurate source for deep sleep and hibernation modes

4. [Tiva™ TM4C123GH6PM Microcontroller Data Sheet]
Cortex M4 Clocking
Clock
Interrupt Concepts
Timer
Timed Cycles
[Tiva™ TM4C123GH6PM Microcontroller Data Sheet]

5. [Tiva™ TM4C123GH6PM Microcontroller Data Sheet]
Cortex M4 Clocking
How the internal system clock is derived from the clock sources: configured in registers OSCSRC and OSCSRC2:
[Tiva™ TM4C123GH6PM Microcontroller Data Sheet]

6. Phase-Lock-Loop
Example SYSDIV (n) values:
n=4 gives 400/(4+1) = 80 MHz
n=7 gives 400/(7+1) = 50MHz
n=9 gives 400/(9+1) = 40MHz
n=15 gives 400/(15+1) = 25MHz
Internal oscillator requires minimal power but is imprecise
External crystal provides stable bus clock
TM4C123 is equipped with 16 MHz crystal and bus clock can be set to a maximum of 80 MHz
[J.Valvano Lec]

7. Exceptions Exceptions include
Resets
Software interrupts
Hardware interrupts
Each exception: associated 32-bit vector that points to the location, where the service routine handling this exception is located
Interrupts and their handling based on priorities are controlled by the NVIC (Nested Vectored Interrupt Controller)

8. Interrupts
An interrupt is the automatic transfer of software execution control to a specific service routine after occurance of a hardware event (trigger) that is asynchronous with the current software execution.
Interrupt triggers:
external I/O device (like a keyboard or printer) or
an internal event (like an op code fault, or a periodic timer.)
[J.Valvano Lec]

9. Interrupts IRQ HW Events Main Program μP Firmware
Interrupt Service Routine (ISR)
IRQ
Context storage
T I M E
Context restore

10. ARM Cortex-M Interrupts
Each potential interrupt source has a separate arm bit
Set for those devices from which it wishes to accept interrupts,
Deactivate in those devices from which interrupts are not allowed
Each potential interrupt source has a separate flag bit
hardware sets the flag when it wishes to request an interrupt
software clears the flag in ISR to signify it is processing the request
Interrupt enable conditions in processor
Global interrupt enable bit, I, in PRIMASK register
Priority level, BASEPRI, of allowed interrupts (0 = all):
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents (masks) the activation of all exceptions with the same or higher priority level as the BASEPRI value (example: BASEPRI=2: IRs with levels 2..7 are prevented)
[J.Valvano Lec]

11. Interrupt Conditions
Four conditions must be true simultaneously for an interrupt to occur:
Arm: control bit for each possible source is set
Enable: interrupts globally enabled (I=0 in PRIMASK)
Level: interrupt level must be lower than BASEPRI
Trigger: hardware action sets source-specific flag
Interrupt remains pending if trigger is set but any other condition is not true
Interrupt serviced once all conditions become true
Need to acknowledge interrupt
Clear the trigger flag or you will get endless interrupts!
[J.Valvano Lec]

12. Interrupt Processing The execution of the main program is interrupted
the current instruction is finished,
suspend execution and push 8 registers (R0-R3, R12, LR, PC, PSR) on the stack
LR set to 0xFFFFFFF9 (indicates interrupt return)
(see: M4 data sheet, Table 2-10, p. 111)
IPSR set to interrupt number (normally, when in main program execution IPSR has the value 0)
sets PC (program counter) to ISR address
The interrupt service routine (ISR) is executed
clears the flag that requested the interrupt
performs necessary operations
communicates using global variables
The main program is resumed when ISR executes BX LR
pulls the 8 registers from the stack
[J.Valvano Lec]

13. IR: Handling Registers
R0-R3: parameters
R4-R11: have to be saved
PRIMASK: general IR enable bit
BASEPRI: IR priority level masking

14. Priority Mask Register
Disable interrupts (I=1)
CPSID I
Enable interrupts (I=0)
CPSIE I
[J.Valvano Lec]

15. Program Status Register
Accessed separately or all at once
Q = Saturation, T = Thumb bit
[J.Valvano Lec]

16. Interrupt Program Status Register (ISPR)
(main program is executed)
Run debugger: - stop in ISR and - look at IPSR
[J.Valvano Lec]

17. Interrupt Context Switch
we are in the main programme
Vector address for GPIO Port C
Interrupt Number 18 corresponds to GPIO Port C
[J.Valvano Lec]

18. 77 vectors in total INTERRUPT VECTORS [J.Valvano Lec] Vector address
Number
IRQ
ISR name in Startup.s
NVIC
Priority bits 0x 14 -2
PendSV_Handler
NVIC_SYS_PRI3_R
23 – 21
0x C 15 -1
SysTick_Handler
31 – 29 0x 16
GPIOPortA_Handler
NVIC_PRI0_R
7 – 5 0x 17 1
GPIOPortB_Handler
15 – 13 0x 18 2
GPIOPortC_Handler
0x C 19 3
GPIOPortD_Handler 0x 20 4
GPIOPortE_Handler
NVIC_PRI1_R 0x 21 5
UART0_Handler 0x 22 6
UART1_Handler
0x C 23 7
SSI0_Handler 0x 24 8
I2C0_Handler
NVIC_PRI2_R 0x 25 9
PWMFault_Handler 0x 26 10
PWM0_Handler
0x C 27 11
PWM1_Handler 0x 28 12
PWM2_Handler
NVIC_PRI3_R 0x 29 13
Quadrature0_Handler 0x 30
ADC0_Handler
0x C 31
ADC1_Handler 0x 32
ADC2_Handler
NVIC_PRI4_R 0x 33
ADC3_Handler 0x 34
WDT_Handler
0x C 35
Timer0A_Handler 0x 36
Timer0B_Handler
NVIC_PRI5_R 0x 37
Timer1A_Handler 0x 38
Timer1B_Handler
0x C 39
Timer2A_Handler
0x000000A0 40
Timer2B_Handler
NVIC_PRI6_R
0x000000A4 41
Comp0_Handler
0x000000A8 42
Comp1_Handler
0x000000AC 43
Comp2_Handler
0x000000B0 44
SysCtl_Handler
NVIC_PRI7_R
0x000000B4 45
FlashCtl_Handler
0x000000B8 46
GPIOPortF_Handler
0x000000BC 47
GPIOPortG_Handler
0x000000C0 48
GPIOPortH_Handler
NVIC_PRI8_R
0x000000C4 49
UART2_Handler
0x000000C8 50
SSI1_Handler
0x000000CC 51
Timer3A_Handler
0x000000D0 52
Timer3B_Handler
NVIC_PRI9_R
0x000000D4 53
I2C1_Handler
0x000000D8 54
Quadrature1_Handler
0x000000DC 55
CAN0_Handler
0x000000E0 56
CAN1_Handler
NVIC_PRI10_R
0x000000E4 57
CAN2_Handler
0x000000E8 58
Ethernet_Handler
0x000000EC 59
Hibernate_Handler
0x000000F0 60
USB0_Handler
NVIC_PRI11_R
0x000000F4 61
PWM3_Handler
0x000000F8 62
uDMA_Handler
0x000000FC 63
uDMA_Error
INTERRUPT VECTORS
77 vectors in total
[J.Valvano Lec]

19. Nested Vectored Interrupt Controller (NVIC)
Hardware unit that coordinates among interrupts from multiple sources
Define priority level of each interrupt source (NVIC_PRIx_R registers)
Separate enable flag for each interrupt source (NVIC_EN0_R and NVIC_EN1_R)
Higher priority interrupts can interrupt lower priority ones
[J.Valvano Lec]

20. NVIC Registers: Priority
High order three bits of each byte define priority
Address
31 – 29
23 – 21
15 – 13
7 – 5
Name
0xE000E400
GPIO Port D
GPIO Port C
GPIO Port B
GPIO Port A
NVIC_PRI0_R
0xE000E404
SSI0, Rx Tx
UART1, Rx Tx
UART0, Rx Tx
GPIO Port E
NVIC_PRI1_R
0xE000E408
PWM Gen 1
PWM Gen 0
PWM Fault
I2C0
NVIC_PRI2_R
0xE000E40C
ADC Seq 1
ADC Seq 0
Quad Encoder
PWM Gen 2
NVIC_PRI3_R
0xE000E410
Timer 0A
Watchdog
ADC Seq 3
ADC Seq 2
NVIC_PRI4_R
0xE000E414
Timer 2A
Timer 1B
Timer 1A
Timer 0B
NVIC_PRI5_R
0xE000E418
Comp 2
Comp 1
Comp 0
Timer 2B
NVIC_PRI6_R
0xE000E41C
GPIO Port G
GPIO Port F
Flash Control
System Control
NVIC_PRI7_R
0xE000E420
Timer 3A
SSI1, Rx Tx
UART2, Rx Tx
GPIO Port H
NVIC_PRI8_R
0xE000E424
CAN0
Quad Encoder 1
I2C1
Timer 3B
NVIC_PRI9_R
0xE000E428
Hibernate
Ethernet
CAN2
CAN1
NVIC_PRI10_R
0xE000E42C
uDMA Error
uDMA Soft Tfr
PWM Gen 3
USB0
NVIC_PRI11_R
0xE000ED20
SysTick
PendSV --
Debug
NVIC_SYS_PRI3_R
[J.Valvano Lec]

21. NVIC Interrupt Enable Registers
Global interrupt configuration with PRIMASK and BASEPRI
Local interrupt configuration: Specific Priority (as shown before and two enable registers – NVIC_EN0_R and NVIC_EN1_R
Each 32-bit register has a single enable bit for a particular device
NVIC_EN0_R control the IRQ numbers 0 to 31 (interrupt numbers 16 – 47)
NVIC_EN1_R control the IRQ numbers 32 to 47 (interrupt numbers 48 – 63)
[J.Valvano Lec]

22. Interrupt Configuration Procedure
Configuration Procedure for interrupts:
Initialize data structures (counters, pointers)
Arm (specify a flag may interrupt)
Configure NVIC
Enable interrupt (NVIC_EN0_R)
Set priority (e.g., NVIC_PRI1_R)
Enable Interrupts
Assembly code CPSIE I
C code EnableInterrupts();
[J.Valvano Lec]

23. Interrupt Service Routine (ISR)
Things you must do in every interrupt service routine
Acknowledge
clear flag that requested the interrupt
SysTick is exception; automatic acknowledge
Maintain contents of R4-R11 (AAPCS)
Communicate via shared global variables
[J.Valvano Lec]

24. Interrupt Events Respond to infrequent but important events
Alarm conditions like low battery power
Error conditions
I/O synchronization
Trigger interrupt when signal on a port changes
Periodic interrupts
Generated by the timer at a regular rate
Systick timer can generate interrupt when it hits zero
Reload value + frequency determine interrupt rate
[J.Valvano Lec]

25. Synchronization
Synchronisation between Main Program and ISR (Interrupt Service Routine):
Semaphore
One thread sets the flag
The other thread waits for, and clears
Here: flag/variable
set in main program
controls if ISR will do
something or not
just set a
Flag in ISR
and give control back to main
Use global variable to communicate
[J.Valvano Lec]

26. Periodic Interrupts Data acquisition samples ADC
Lab 8 (Valvano) will sample at a fixed rate
Signal generation output to DAC
Audio player (we use the Systick interrupt to write samples out periodically in Lab 6 (Valvano))
Communications
Digital controller
FSM
Linear control system
Demo PeriodicSystickInts starter C code (in Valvano’s Course)
[J.Valvano Lec]

27. Microcontrollers: Timers
Control System:
actuating
variable
control
variable
Set
value
Control
Algorithm -
A/D
Sensors
D/A
Actuators
Physical Environment/
Process
Sample
Time Ts
control
variable t
sample
point
Output of
Actuating variable
Computation time
≤ 0.1 Ts

28. [Tiva™ TM4C123GH6PM Microcontroller Data Sheet]
SysTick Timer
SysTick: A SysTick exception is an exception that the system timer generates when it reaches zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor can use this exception as system tick.
The timer consists of three registers:
SysTick Control and Status (STCTRL): A control and status register to configure its clock, enable the counter, enable the SysTick interrupt, and determine counter status.
SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the counter's wrap value.
SysTick Current Value (STCURRENT): The current value of the counter.
[Tiva™ TM4C123GH6PM Microcontroller Data Sheet]

29. SysTick Timer Timer/Counter operation
24-bit counter decrements at bus clock frequency
With 80 MHz bus clock, decrements every 12.5 ns
Counting is from n  0
Setting n appropriately will make the counter a modulo n+1 counter. That is:
next_value = (current_value-1) mod (n+1)
Sequence: n,n-1,n-2,n-3… 2,1,0,n,n-1…
Modulo (mod or %) operation gives the remainder: (a mod n) is the remainder when a is divided by n.
When a < n, (a mod n) is simply a.
When current_value reaches 0, then the next value is [(0-1)mod (n+1)] = -1 mod (n+1) = n
That is the counter gets reset to max value n after it reaches 0.
[J.Valvano Lec]

30. SysTick Timer Initialization (4 steps)
Flag:
0 = The SysTick timer has not counted to 0 since the last time
this bit was read.
1=The SysTick timer has counted to 0 since the last time this bit was read.
Initialization (4 steps)
Step1: Clear ENABLE to stop counter
Step2: Specify the RELOAD value
Step3: Clear the counter via NVIC_ST_CURRENT_R
Step4: Set NVIC_ST_CTRL_R
CLK_SRC = 1 (bus clock is the only option)
INTEN = 0 for no interrupts
ENABLE = 0 to enable
RELOAD value is the value to load into the counter (reset) every time it hits zero, i.e. the n value from the previous slide
[J.Valvano Lec]

31. SysTick Timer 24-bit Countdown Timer SysTick_Init
; disable SysTick during setup
LDR R1, =NVIC_ST_CTRL_R
MOV R0, # ; Clear Enable
STR R0, [R1]
; set reload to maximum reload value
LDR R1, =NVIC_ST_RELOAD_R
LDR R0, =0x00FFFFFF; ; Specify RELOAD value
STR R0, [R1] ; reload at maximum
; writing any value to CURRENT clears it
LDR R1, =NVIC_ST_CURRENT_R
MOV R0, #0
STR R0, [R1] ; clear counter
; enable SysTick with core clock
MOV R0, #0x ; Enable but no interrupts (later)
STR R0, [R1] ; ENABLE and CLK_SRC bits set
BX LR
24-bit Countdown Timer
You could make the Timer be a 16-bit timer by changing the RELOAD value to be 0x0000FFFF. We will see however there is no good reason to this.
… according to register structure being presented on previous slide
SysTick Counter starts to count now since bit 0 is set to 1
[J.Valvano Lec]

32. SysTick Timer ;------------SysTick_Wait------------
; Time delay using busy wait.
; Input: R0 delay parameter in units of the core clock
; MHz(12.5 nsec each tick)
; Output: none
; Modifies: R1
SysTick_Wait
SUB R0, R0, #1 ; delay-1
LDR R1, =NVIC_ST_RELOAD_R
STR R0, [R1] ; time to wait
LDR R1, =NVIC_ST_CURRENT_R
STR R0, [R1] ; any value written to CURRENT clears
LDR R1, =NVIC_ST_CTRL_R
SysTick_Wait_loop
LDR R0, [R1] ; read status
ANDS R0, R0, #0x ; bit 16 is COUNT flag
BEQ SysTick_Wait_loop ; repeat until flag set
BX LR
delay-1 as initialisation value,
because it counts down to 0)
S: sets flags
BEQ: branch,
if zero flag is set flags
[J.Valvano Lec]

33. volatile is being used for variables which values may change unexpectedly (no normal compiler variable lifetime analysis possible)
SysTick Timer in C
#define NVIC_ST_CTRL_R(*((volatile uint32_t *)0xE000E010))
#define NVIC_ST_RELOAD_R(*((volatile uint32_t *)0xE000E014))
#define NVIC_ST_CURRENT_R(*((volatile uint32_t *)0xE000E018))
void SysTick_Init(void){
NVIC_ST_CTRL_R = 0; // 1) disable SysTick during setup
NVIC_ST_RELOAD_R = 0x00FFFFFF; // 2) maximum reload value
NVIC_ST_CURRENT_R = 0; // 3) any write to CURRENT clears it
NVIC_ST_CTRL_R = 0x ; // 4) enable SysTick with core clock }
// The delay parameter is in units of the 80 MHz core clock(12.5 ns)
void SysTick_Wait(uint32_t delay){
NVIC_ST_RELOAD_R = delay-1; // number of counts
NVIC_ST_CURRENT_R = 0; // any value written to CURRENT clears
while((NVIC_ST_CTRL_R&0x )==0){ // wait for flag
// Call this routine to wait for delay*10ms
void SysTick_Wait10ms(uint32_t delay){
unsigned long i;
for(i=0; i<delay; i++){
SysTick_Wait(800000); // wait 10ms
dereference operator
Type-cast to pointer on volatile 32-bit unsigned integer
delay-1 because it counts down to 0)
Bard, Gerstlauer, Valvano, Yerraballi
[J.Valvano Lec]

34. Control Loops with SysTick Timer
Implementation of a Control System (e.g. in a closed loop control in a mechatronic system):
Calculate the amount of clock cyles from sample point to sample point
Initialize SysTick timer
Enable Interrupt for systick timer
Control algorithm will be completely executed within ISR (should have highest priority)
Main program handles user interface and communication

35. Microcontrollers: Watchdog
Source: shaunthesheep.be
Special Timer, generating in interrupt when expiring (timeout) detection of SW faults
Watchdog can be refreshed in the main loop of the program and if this refresh is not reached (program hangs), a defined reset is generated

36. Microcontrollers: Watchdog
TM4C123GH6PM two Watchdog Timer Modules:
Watchdog Timer 0: clocked by system clock
Watchdog Timer 1: clocked by PIOSC
The two modules are identical except that WDT1 is in a different clock domain, and therefore requires synchronizers. As a result, WDT1 has a bit defined in the Watchdog Timer Control (WDTCTL) register to indicate when a write to a WDT1 register is complete. Software can use this bit to ensure that the previous access has completed before starting the next access.
[Tiva™ TM4C123GH6PM Microcontroller Data Sheet]

37. Microcontrollers: Watchdog
The two Watchdog Timer modules of the TM4C123GH6PM controller have the following features:
32-bit down counter with a programmable load register
Separate watchdog clock with an enable
Programmable interrupt generation logic with interrupt masking and optional NMI function
Lock register protection from runaway software
Reset generation logic with an enable/disable
User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug
[Tiva™ TM4C123GH6PM Microcontroller Data Sheet]

38. Microcontrollers: Watchdog
Watchdog architecture: block diagram
[Tiva™ TM4C123GH6PM Microcontroller Data Sheet]

39. Microcontrollers: Watchdog
To use the WDT, its peripheral clock must be enabled by setting the Rn bit in the Watchdog Timer
Run Mode Clock Gating Control (RCGCWD) register, see datasheet page 337.
The Watchdog Timer is configured using the following sequence:
Load the WDTLOAD register with the desired timer load value.
If WDT1, wait for the WRC bit in the WDTCTL register to be set (synchronisation, since in other clock domain).
If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register.
If WDT1, wait for the WRC bit in the WDTCTL register to be set.
Set the INTEN bit in the WDTCTL register to enable the Watchdog, enable interrupts, and lock the control register.

40. Cyclic Output: PWM
Cyclic output, with defined signal-on and signal-off phases:
Duty cyle: lenght of on phase related to length of cycle (time, clock cycles)
cycle length
on phase
off phase

41. Cyclic Output: PWM
PWM + Low Pass Filter = Digital2Analog Converter: duty cycle is proportional to generated analog voltage
Example: 3.3 V PWM output waveform Duty cycle 100%: analog voltage = 3.3V Duty cycle 50%: analog voltage = 1.65V Duty cycle 10%: analog voltage = 0.33V
Low Pass Filter: simple RC element can be used; in many cases the connected actuator itself has a lowpass characteristics (e.g. a motor), then no specific low-pass filter is needed

42. Conclusion Cyclic Timing Referenc: Clock
Time is generated by passing a certain amount of clock cycles  counters
Multithreading by interrupts
Watchdogs: mechanism to detect „hanging states“ in SW and reset the device