1. Lab 9 ASIC Logic 第八組 R91943003 陳方玉 R91943007 陳建宏 R91943072 柯鴻洋
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2. Outline Introduction to the ASIC Logic Experiment Steps
RGB to YUV Conversion HW Module
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3. Outline Introduction to the ASIC Logic Experiment Steps
RGB to YUV Conversion HW Module
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4. Basics for Prototyping with Logic Modules
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5. Basic Platforms: AHB
Basic Platforms: AHB and ASB
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6. Logic Module Registers
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7. Outline Introduction to the ASIC Logic Experiment Steps
RGB to YUV Conversion HW Module
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8. Steps for Example 1
(1)Flash the LEDs on the Logic Module from left to right.
(2)The speed of flashing the LEDs from left to right can be
set by changing the configuration of the 8-way switch.
(3) Comparison of programming FPGA
FPGA version: programs the FPGA by writing the bit stream image into the FPGA directly. The image will start running right after programming into the FPGA.
Flash version: programs the FPGA by writing the bit stream image into the flash. The image will start after next power up of the development system.
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9. Steps of Example 1 Control Clock Frequency by 8-Way Switches
Setting Clock Frequency
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10. These steps are the same as in experiment 8:
Steps of Example 2
(1)Determine the DRAM size on the Core Module and set
up the system controller
(2)Make sure the Logic Module is present in the AP expansion
position
(3)Report module information
(4)Set the Logic Module clock frequencies
(5)Test SSRAM for word, halfword, and byte accesses
(6)Test the custom design device’s single register access
Flash the LED
(7)Remain in a loop that displays the 8-way switch value of the
Logic Modules on its LEDs.
These steps are the same as in experiment 8:
AMBA BUS
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11. Reminder
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12. Remember to set the third switch on
Reminder
Remember to set the third switch on
Program FPGA from Image 0
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13. Experiment Steps:example2
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14. Outline Introduction to the ASIC Logic Experiment Steps
RGB to YUV Conversion HW Module
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15. RGB to YUV Conversion Implement with pure software.
Implement with hardware.
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16. Memory Definition
LM_MYIP=0xC
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17. RGB to YUV Program (1)Add MYIP.v into top module.
(2)Modify AHBDecoder.v.
(3)Modify AHBMuxS2M.v.
(4)Modify AHBAHBTop.v.
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18. Architecture
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19. Modification of AHBAHBTOP.v
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20. Modification of AHBDecoder.v
RGB to YUV Program
Modification of AHBDecoder.v
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21. Modification of AHBMuxS2M.v
RGB to YUV Program
Modification of AHBMuxS2M.v
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22. MYIP.v modified from AHBZBTRAM.v
MYIP.v is modified from AHBZBTRAM.v
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23. MYIP.v modified from AHBZBTRAM.v
Divide HWDATA into r,g,b parts
MYIP.v is modified from AHBZBTRAM.v
Combine y,u,v into output HRDATA
(2:1:1)
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24. Logic.c Initialize LM Module Software Implementation
Write RGB value into LM_MYIP
and read YUV as data_myip
Post processor for data_myip
to read out YUV value
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25. Set Registor for LM_MYIP
Logic.h
Set Registor for LM_MYIP
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26. Result of Pure Software Implementation
Input parameters
Result of Pure Software Implementation
Result of Hardware Implementation
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27. Verilog Coding Confusion btw. Signed and Unsigned Multiplication
Truncation
負數的二進位轉換
小數點對齊
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28. Reference Integrator ASIC Platform [DUI_0098B_AP_UG]
System Memory Map [DUI_0098B_AP_UG 4.1]
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