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Overview of SHARC processor ADSP-2106X Memory Operations

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Presentation on theme: "Overview of SHARC processor ADSP-2106X Memory Operations"— Presentation transcript:

1 Overview of SHARC processor ADSP-2106X Memory Operations
* 07/16/96 This presentation will probably involve audience discussion, which will create action items. Use PowerPoint to keep track of these action items during your presentation In Slide Show, click on the right mouse button Select “Meeting Minder” Select the “Action Items” tab Type in action items as they come up Click OK to dismiss this box This will automatically create an Action Item slide at the end of your presentation with your points entered. Overview of SHARC processor ADSP-2106X Memory Operations M. R. Smith, Electrical and Computer Engineering, University of Calgary, Alberta, Canada ucalgary.ca *

2 To be tackled today Reference sources
Memory configuration and operations Sample instructions Some warnings of expected errors Code review and code review standards 4/19/2019 ENCM Review of SHARC Processor Copyright

3 Reference Sources ADSP-2106x SHARC User’s Manual 2nd edition, Analog Devices -- provided to everybody ENCM515 SHARC Reference card ENCM515 Course, Reference and Laboratory Notes Check web-pages for links to VisualDSP++, Compiler, Assembler, Linker and other tools Also see ECE-ADI-Project (link from Dr. Smith Home Page) SHARC Navigator Tutorial Tool See January 2004 web pages for link – shows basic assembly language operations using simple animation 4/19/2019 ENCM Review of SHARC Processor Copyright

4 Picture Source SHARC Navigator Tutorial Tool T. Talik Alukaidey Dept. of EEE Uninversity of Hertfordshire, Hatfield, U.K. 4/19/2019 ENCM Review of SHARC Processor Copyright

5 ADSP-2106x Core Architecture
* ADSP-2106x Core Architecture 07/16/96 DAG 2 8 x 4 x 24 DAG 1 8 x 4 x 32 CACHE MEMORY 32 x 48 PROGRAM SEQUENCER PMD BUS DMD BUS 24 PMA BUS PMD DMD PMA 32 DMA BUS DMA 48 40 JTAG TEST & EMULATION FLAGS FLOATING & FIXED-POINT MULTIPLIER, FIXED-POINT ACCUMULATOR 32-BIT BARREL SHIFTER FLOATING-POINT & FIXED-POINT ALU REGISTER FILE 16 x 40 BUS CONNECT TIMER *

6 2106X Memory Accesses Under the right conditions -- 3 memory accesses at same time Program Memory, Data Memory, Instruction Cache PLUS up to 2 ALU + 1 MAC operations at the same time PLUS background DMA activity 4/19/2019 ENCM Review of SHARC Processor Copyright

7 Data Address Generators -- DAG
There is only 1 memory, but it is broken into 2 sections DAG1 -- best for accessing Data memory section (0 -- 7) DAG2 -- best for accessing Program memory section ( ) MUST be used in this fashion for simultaneous memory ops Also an alternate set of DAGs (SHADOW DAGs) 4/19/2019 ENCM Review of SHARC Processor Copyright

8 Register and Register Ops in DAG1
SPECIAL CIRCBUFFER STUFF SPECIAL FFT BIT 4/19/2019 ENCM Review of SHARC Processor Copyright

9 DAG register info Index registers Modify registers M0 -- M7, M8 -- M15
I0 -- I7 (dm -- data mem), I8 -- I15 (pm -- program mem) “like” 68K address registers A0 -- A6 Modify registers M0 -- M7, M8 -- M15 Can be offset registers (c.f 68K (4, SP) Can be used for high speed post increment Special Hardware for Circular Buffers Base registers B0 -- B7, B8 -- B15 Length registers L0 -- L7, L8 -- L15 See labs and associated lectures SEE REF-CARD 4/19/2019 ENCM Review of SHARC Processor Copyright

10 Some memory access instructions
SEE REF-CARD Add the following to your reference sheet ureg = <data32> 4/19/2019 ENCM Review of SHARC Processor Copyright

11 Special hardware addressing modes
SEE REF-CARD 4/19/2019 ENCM Review of SHARC Processor Copyright

12 Example code // Global array long int array[4] = {2, 3, 4, 5};
// Program segment long int sum = 0; sum = sum + array[0]; sum = sum + array[1]; sum = sum + array[2]; sum = sum + array[3]; 4/19/2019 ENCM Review of SHARC Processor Copyright

13 Example code .section/dm seg_dmda; // Global array
Indicates placed in data memory data section .section/pm seg_pmco; Indicates placed in program memory code section // Global array long int array[4] = {2, 3, 4, 5}; // Program segment long int sum = 0; sum = sum + array[0]; sum = sum + array[1]; sum = sum + array[2]; sum = sum + array[3]; 4/19/2019 ENCM Review of SHARC Processor Copyright

14 Example code .section/dm seg_dmda; // Global array
// 68K style .GLOBAL _array; _array: .var = {2,3,4,5}; // Alternate style .var _array[] = {2,3,4,5}; // Can also include a “data file” .var _array[ ] = “file.dat”; // Global array long int array[4] = {2, 3, 4, 5}; // Program segment long int sum = 0; sum = sum + array[0]; sum = sum + array[1]; sum = sum + array[2]; sum = sum + array[3]; 4/19/2019 ENCM Review of SHARC Processor Copyright

15 Example code – poor approach
#define sum_R0 R0 #define temp_R1 R1 sum_R0 = 0; temp_R1 = dm(_array); sum_R0 = sum_R temp_R1; temp_R1 = dm(_array + 1); sum_R0 = sum_R temp_R1; temp_R1 = dm(_array + 2); etc. // Global array long int array[4] = {2, 3, 4, 5}; // Program segment long int sum = 0; sum = sum + array[0]; sum = sum + array[1]; sum = sum + array[2]; sum = sum + array[3]; 4/19/2019 ENCM Review of SHARC Processor Copyright

16 Example code – correct, but poor
.section/dm seg_dmda; .GLOBAL _array; .var _array[ ] = {2,3,4,5}; .section/pm seg_pmco; #define sum_R0 R0 #define temp_R1 R1 #define array_pt_I4 I4 sum_R0 = 0; array_pt_I4 = _array; temp_R1 = dm(0, array_pt_I4); sum_R0 = sum_R0 + temp_R1; temp_R1 = dm(1, array_pt_I4); temp_R1 = dm(2, array_pt_I4); // Global array long int array[4] = {2, 3, 4, 5}; // Program segment long int sum = 0; sum = sum + array[0]; sum = sum + array[1]; sum = sum + array[2]; sum = sum + array[3]; 4/19/2019 ENCM Review of SHARC Processor Copyright

17 Example code -- INVALID
.section/dm seg_dmda; .GLOBAL _array; .var _array[ ] = {2,3,4,5}; .section/pm seg_pmco; #define sum_R0 R0 #define temp_R1 R1 #define array_pt_I4 I4 sum_R0 = 0; array_pt_I4 = _array; temp_R1 = dm(array_pt_I4, 0); sum_R0 = sum_R0 + temp_R1; temp_R1 = dm(array_pt_I4, 1); temp_R1 = dm(array_pt_I4, 2); // Global array long int array[4] = {2, 3, 4, 5}; // Program segment long int sum = 0; sum = sum + array[0]; sum = sum + array[1]; sum = sum + array[2]; sum = sum + array[3]; 4/19/2019 ENCM Review of SHARC Processor Copyright

18 Example code -- INVALID
sum_R0 = 0; array_pt_I4 = _array; temp_R1 = dm(array_pt_I4, 0); sum_R0 = sum_R0 + temp_R1; temp_R1 = dm(array_pt_I4, 1); temp_R1 = dm(array_pt_I4, 2); POST-MODIFY OPERATIONS SIMILAR TO 68K increment MOVE.L (A0)+, D1 temp_R1 = DataMEM[array_pt_I4]; Then array_pt_I4 = array_pt_I4 + 0; array_pt_I4 = array_pt_I4 + 1; array_pt_I4 = array_pt_I4 + 2; Sum of locations 0, 0, 1 with Pointer left at location 3 of array 4/19/2019 ENCM Review of SHARC Processor Copyright

19 Better designed code // Global array long int array[4] = {2, 3, 4, 5};
long int sum = 0; long int temp_pt = array; sum += *temp_pt++; USEABLE IN A LOOP // Global array long int array[4] = {2, 3, 4, 5}; // Program segment long int sum = 0; sum = sum + array[0]; sum = sum + array[1]; sum = sum + array[2]; sum = sum + array[3]; 4/19/2019 ENCM Review of SHARC Processor Copyright

20 Better designed code -- solution
.section/pm seg_pmco; #define sum_R0 R0 #define temp_R1 R1 #define temp_pt_I4 I4 #include “cregister_defs.i” sum_R0 = 0; temp_pt_I4 = _array; temp_R1 = dm(temp_pt_I4, DMPLUS1); sum_R0 = sum_R0 + temp_R1; // Global array long int array[4] = {2, 3, 4, 5}; // Program segment long int sum = 0; long int temp_pt = array; sum += *temp_pt++; 4/19/2019 ENCM Review of SHARC Processor Copyright

21 Why does it work #include “cregister_defs.i” temp_R1 = dm(temp_pt_I4, DMPLUS1); When linking to “C/C++” code then certain DAG registers are set aside (VisualDSP++ coding convention) to work more efficiently with common “C/C++” memory operations M5 set to 0 during “C/C++” startup M6 set to 1 during “C/C++” startup M7 set to –1 during “C/C++” startup We have defined certain mnemonics for easier “C/C++/assembly language usage #define DMPLUS1 M6 4/19/2019 ENCM Review of SHARC Processor Copyright

22 Why not code as // Global array long int array[4] = {2, 3, 4, 5};
.section/pm seg_pmco; #define sum_R0 R0 #define temp_R1 R1 #define temp_pt_I4 I4 #include “cregister_defs.i” sum_R0 = 0; temp_pt_I4 = _array; temp_R1 = dm(temp_pt_I4, 1); sum_R0 = sum_R0 + temp_R1; Using the constant 1 takes up more instruction bits (6 bits) than using register M6 and therefore this instruction can be used with LESS parallel instructions // Global array long int array[4] = {2, 3, 4, 5}; // Program segment long int sum = 0; long int temp_pt = array; sum += *temp_pt++; 4/19/2019 ENCM Review of SHARC Processor Copyright

23 Example – you tackle // Global array float array[4] = {2, 3, 4, 5};
Use this style of coding float sum = 0; float temp_pt = array; sum += *temp_pt++; USEABLE IN A LOOP // Global array float array[4] = {2, 3, 4, 5}; // Program segment float sum = 0; sum = sum + array[0]; sum = sum + array[1]; sum = sum + array[2]; sum = sum + array[3]; 4/19/2019 ENCM Review of SHARC Processor Copyright

24 To be tackled today Reference sources
Memory configuration and operations Sample instructions Some warnings of expected errors Code review and code review standards 4/19/2019 ENCM Review of SHARC Processor Copyright

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