1. Effects of LER on MOSFET Electrical Behavior
SFR Workshop
November 8, 2000
Shiying Xiong, Jeffrey Bokor
Berkeley, CA
2001 GOAL: Complete device simulations for AMD device designs at 100nm, 70 nm, and 50 nm gate length, including effect of isolation roughness by 9/30/2001.
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2. Motivation Problems with LER Possible effects on devices
Channel length variation
Edge Electric field
Enhanced dopant diffusion
Possible effects on devices
Change of device parameters from target values
( leakage, driving current, swing and etc.)
Enhanced hot carrier degradation
Isolation problem
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3. LER device simulation Base device design LER model
0.1um SOI NMOSFET with self-aligned source and drain
Gate Length = 0.1um
Buried Oxide = 100 nm
Si Film Thickness = 250Å
Gate Oxide = 30 Å
Channel doping and halo selected to make Vt ~ 0.4V
Swing mV/decade
Vdmax = 1.1V
LER model
Digitized red noise
LER parameters:
RMS
Correlation Length ( ~1/fcutoff )
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4. Simulation results Device with diffusion (Source side is rough)
After diffusion:
Junction is smoothed
Leff is reduced
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5. Simulation Results LER enhanced dopant diffusion
Junction extracted from device simulation
Further proof: 2D diffusion of doping boundary with LER
Significant enhanced diffusion when Lc smaller or comparable with diffusion SQRT(Dt)
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6. Do we really need 3D simulations?
2D simulation of abrupt junction devices of different channel length
Small
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7. Do we really need 3D simulations?
Try
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8. Starting experiments Cooperation Project with AMD
SEM current scan over line
step one: LER extraction
Rebuilt of the top line edge of ~50nm bottom width line
Average top width: 39.3nm, RMS1=2.5nm, RMS2=2.7nm, RMSW=2.7nm
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9. Conclusion Proposal 2002-2003 Milestones
For device with diffusion, current increase was dominated by LER enhanced dopant diffusion and effective channel length shortening, which also bring increase in overlap capacitance
For device with LER, current is larger than the current integration of 2D device with varying channel length. Enhanced edge field and diffusion are 3D effect.
Proposal Milestones
Wafers processed at AMD finished with varying, and well-characterized LER by 9/30/2002.
Device characterization on AMD wafers completed and data analyzed by 9/30/2003
11/8/2000