1. Lecture #18 OUTLINE Reading Continue small signal analysis
Logic functions
NMOS logic gates
The CMOS inverter
Reading
Rabaey et al.: Chapter 5.2
Hambley: Chapter

2. Digital Signals
For a digital signal, the voltage must be within one of two ranges in order to be defined:
Positive Logic:
“low” voltage  logic state 0
“high” voltage  logic state 1
VDD
VOH
“1”
VIH
increasing
voltage
undefined region
VIL
“0”
VOL
0 Volts

3. Logic Functions, Symbols, & Notation
TRUTH
NAME SYMBOL NOTATION TABLE A F 1
“NOT” A F
F = A A B F 1 A
“OR” F
F = A+B B A B F 1 A
“AND” F
F = A•B B

4. A “NOR” F F = A+B B A “NAND” F F = A•B B A “XOR” F F = A + B B A B F 11 A
“NOR” F
F = A+B B A B F 1 A
“NAND” F
F = A•B B A B F 1 A
“XOR”
(exclusive OR) F
F = A + B B

5. NMOS Inverter (“NOT” Gate)
Circuit:
Voltage-Transfer Characteristic
vOUT
VDD F A iD
vIN = VDD
increasing
vGS = vIN > VT
vIN VT
VDD
VDD/RD
VDD A F 1
vDS
vGS = vin  VT

6. Noise Margins Noise margin high Noise margin low
Definition of Input Levels
Definition of Noise Margins
logic
swing
Vsw
VOL
VOH
Noise margin high
Noise margin low

7. Output is low only if both inputs are high
NMOS NAND Gate
Output is low only if both inputs are high
VDD RD F A
Truth Table A B F 1 B

8. Output is low if either input is high
NMOS NOR Gate
Output is low if either input is high
VDD RD F A B
Truth Table A B F 1

9. Disadvantages of NMOS Logic Gates
Large values of RD are required in order to
achieve a low value of VOL
keep power consumption low
Large resistors are needed, but these take up a lot of space.
One solution is to replace the resistor with an NMOSFET that is always on.

10. The CMOS Inverter: Intuitive Perspective
CIRCUIT
SWITCH MODELS
VDD
VIN
VOUT S D G
VDD
VDD Rp
VOUT
VOUT
VOL = 0 V
VOH = VDD Rn
Low static power consumption, since
one MOSFET is always off in steady state
VIN = VDD
VIN = 0 V

11. CMOS Inverter Voltage Transfer Characteristic
N: sat
P: sat
VOUT
N: off
P: lin C
VDD
N: sat
P: lin A B D E
N: lin
P: sat
N: lin
P: off
VIN
VDD

12. CMOS Inverter Load-Line Analysis
VGSp=VIN-VDD – +
VIN = VDD + VGSp –
VDSp=VOUT-VDD +
VOUT = VDD + VDSp
IDn=-IDp
increasing
VIN
VIN = 0 V
VIN = VDD
IDn=-IDp
increasing
VIN
VOUT=VDSn
VDD
VDSp = 0
VDSp = - VDD

13. CMOS Inverter Load-Line Analysis: Region A
VGSp=VIN-VDD – +
VIN  VTn –
VDSp=VOUT-VDD +
IDn=-IDp
IDn=-IDp
VOUT=VDSn
VDD

14. CMOS Inverter Load-Line Analysis: Region B
VGSp=VIN-VDD – +
VDD/2 > VIN > VTn –
VDSp=VOUT-VDD +
IDn=-IDp
IDn=-IDp
VOUT=VDSn
VDD

15. CMOS Inverter Load-Line Analysis: Region D
VGSp=VIN-VDD – +
VDD – |VTp| > VIN > VDD/2 –
VDSp=VOUT-VDD +
IDn=-IDp
IDn=-IDp
VOUT=VDSn
VDD

16. CMOS Inverter Load-Line Analysis: Region E
VGSp=VIN-VDD – +
VIN > VDD – |VTp| –
VDSp=VOUT-VDD +
IDn=-IDp
IDn=-IDp
VOUT=VDSn
VDD