1. Unit 13 Analysis of Clocked Sequential Circuits
Ku-Yaw Chang
Assistant Professor, Department of Computer Science and Information Engineering
Da-Yeh University

2. Analysis of Clocked Sequential Circuits
Outline
13.1 A Sequential Parity Checker
13.2 Analysis by Signal Tracing and Timing Charts
13.3 State Tables and Graphs
13.4 General Models for Sequential Circuits
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Analysis of Clocked Sequential Circuits

3. Analysis of Clocked Sequential Circuits
State Tables
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Analysis of Clocked Sequential Circuits

4. Analysis of Clocked Sequential Circuits
State Graph
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Analysis of Clocked Sequential Circuits

5. Construct the State Table
Determine the flip-flop input equations and the output equations from the circuit.
Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q+ = D T flip-flop Q+ = T  Q :
Plot a next-state map for each flip-flop.
Combine these maps to form the state table.
A transition table
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Analysis of Clocked Sequential Circuits

6. Analysis of Clocked Sequential Circuits
First Example
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Analysis of Clocked Sequential Circuits

7. Construct the State Table
Determine the flip-flop input equations and the output equations from the circuit.
Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q+ = D T flip-flop Q+ = T  Q :
Plot a next-state map for each flip-flop.
Combine these maps to form the state table.
A transition table
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Analysis of Clocked Sequential Circuits

8. Construct the State Table
Determine the flip-flop input equations and the output equations from the circuit.
DA = X  B’
DB = X + A
Z = A  B
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Analysis of Clocked Sequential Circuits

9. Construct the State Table
Determine the flip-flop input equations and the output equations from the circuit.
Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q+ = D T flip-flop Q+ = T  Q :
Plot a next-state map for each flip-flop.
Combine these maps to form the state table.
A transition table
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Analysis of Clocked Sequential Circuits

10. Construct the State Table
Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q+ = D D-CE flip-flop Q+ = D · CE + Q · CE’ T flip-flop Q+ = T  Q S-R flip-flop Q+ = S + R’Q J-K flip-flop Q+ = JQ’ + K’Q
A+ = X  B’
B+ = X + A
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Analysis of Clocked Sequential Circuits

11. Construct the State Table
Determine the flip-flop input equations and the output equations from the circuit.
Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q+ = D T flip-flop Q+ = T  Q :
Plot a next-state map for each flip-flop.
Combine these maps to form the state table.
A transition table
2004/05/24
Analysis of Clocked Sequential Circuits

12. Construct the State Table
Plot a next-state map for each flip-flop.
A+ = X  B’
B+ = X + A
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Analysis of Clocked Sequential Circuits

13. Construct the State Table
Determine the flip-flop input equations and the output equations from the circuit.
Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q+ = D T flip-flop Q+ = T  Q :
Plot a next-state map for each flip-flop.
Combine these maps to form the state table.
A transition table
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Analysis of Clocked Sequential Circuits

14. Construct the State Table
Combine these maps to form the state table.
A transition table
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Analysis of Clocked Sequential Circuits

15. Analysis of Clocked Sequential Circuits
Moore State Graph
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Analysis of Clocked Sequential Circuits

16. Analysis of Clocked Sequential Circuits
Second Example
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Analysis of Clocked Sequential Circuits

17. Construct the State Table
Determine the flip-flop input equations and the output equations from the circuit.
JA = XB, KA = X
JB = X, KB = XA
Z = XB’+XA+X’A’B
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Analysis of Clocked Sequential Circuits

18. Construct the State Table
Derive the next-state equation for each flip-flop from its input equations, using one of the following relations: D flip-flop Q+ = D D-CE flip-flop Q+ = D · CE + Q · CE’ T flip-flop Q+ = T  Q S-R flip-flop Q+ = S + R’Q J-K flip-flop Q+ = JQ’ + K’Q
A+ = JAA’ + KA’A = XBA’ + X’A
B+ = JBB’ + KB’B = XB’ + (AX)’B = XB’+ X’B + A’B
Z = X’A’B + XB’ + XA
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Analysis of Clocked Sequential Circuits

19. Construct the State Table
Plot a next-state and output map.
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Analysis of Clocked Sequential Circuits

20. Construct the State Table
Combine these maps to form the state table.
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Analysis of Clocked Sequential Circuits

21. Analysis of Clocked Sequential Circuits
Mealy State Graph
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Analysis of Clocked Sequential Circuits

22. Analysis of Clocked Sequential Circuits
Third Example
Serial Adder xi yi ci
ci+1 si 1
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Analysis of Clocked Sequential Circuits

23. Analysis of Clocked Sequential Circuits
Timing Diagram
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Analysis of Clocked Sequential Circuits

24. Analysis of Clocked Sequential Circuits
Serial Adder
Initially the carry flip-flop must be cleared
C0=0
Start by adding the least-significant (rightmost) bits in each word.
Reading the sum output just before the rising edge of the clock
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Analysis of Clocked Sequential Circuits

25. Analysis of Clocked Sequential Circuits
State Graph
A Mealy machine
Inputs: xi and yi
Output: si
Two states represent a carry (ci)
S0 for 0 and S1 for 1
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Analysis of Clocked Sequential Circuits

26. Multiple Inputs and Outputs
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Analysis of Clocked Sequential Circuits

27. Multiple Inputs and Outputs
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Analysis of Clocked Sequential Circuits