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Chapter 18
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Figure 18.1 CUDA vector addition from Chapter 3.
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Figure 18.2 Vector addition in C++ AMP.
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Figure 18.3 Base coulomb potential calculation code for a 2D slice.
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Figure 18.4 Explicit memory and copy management.
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Figure 18.5 Concurrent host/accelerator execution.
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Figure 18.6 Overlapped accelerator and host processing.
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Figure 18.7 Example of finding an accelerator.
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Figure 18.8 Explicit accelerator use.
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Figure 18.9 Explicit accelerator with asynchronous transfers.
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Figure Tiled matrix multiplication; compare Figure 5.12.
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Figure Illustration of tiling 20×20 compute domain.
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Figure Example of types from concurrency::graphics.
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Figure Example DirectX interop—rotate vertex list.
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