Presentation is loading. Please wait.

Presentation is loading. Please wait.

Buffered Steiner Trees for Difficult Instances

Published byElizabeth Allen Modified over 5 years ago

Similar presentations

Presentation on theme: "Buffered Steiner Trees for Difficult Instances"— Presentation transcript:

1 Buffered Steiner Trees for Difficult Instances
Charles J. Alpert, Gopal Gandham, Milos Hrkic, John Lillis, Jiang Hu, Andrew B. Kahng, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, Andrew J. Sullivan

2 Min-Cost Steiner Tree Late 1980s

3 Timing-driven Steiner Tree
Early 1990s

4 Buffered Steiner Tree Mid 1990s

5 Blockage Aware Trees Present

6 Ripping out Synthesis Trees
Ugly pre-PD buffered trees Inverted sinks Trivial van Ginneken/Lillis change Normal sinks: one positive candidate Inverted sinks: one negative candidate No big deal

7 Or Is It? _ +

8 But Look What Happens _ +

9 Buffer Aware Trees

10 The Texas Two Step Optimal Unrouted net with placed pins Construct
Buffered Steiner Tree Construct Steiner Tree Dynamic Programming Buffer Insertion Simultaneous Tree Construction And Buffer Insertion Optimal

11 C-Tree Algorithm A-, B-, H-, O-, P-, trees taken Cluster sinks by
Polarity Manhattan distance Criticality Two-level tree Form tree for each cluster Form top-level tree

12 C-Tree Example

13 Net n8702 (44 sinks) C-Tree (9) 258 11 4386 0.9 C-Tree (2) 355 9 7688
Algorithm Worst slack buffers wire CPU Time C-Tree (9) 258 11 4386 0.9 C-Tree (2) 355 9 7688 1.5 Flat C-Tree -101 26 4061 1.4 P-Tree 99 19 4089 4.1 BP-Tree 295 21 4119 861

14 Net n8702

15 Flat C-Tree

16 C-Tree 4 clusters

17 C-Tree 2 clusters

18 Difficult Steiner Instances
Polarity/size makes it hard 3d trade-off Timing Buffers Wire length Work on it!

Download ppt "Buffered Steiner Trees for Difficult Instances"

Similar presentations

Porosity Aware Buffered Steiner Tree Construction C. Alpert G. Gandham S. Quay IBM Corp M. Hrkic Univ Illinois Chicago J. Hu Texas A&M Univ.

Porosity Aware Buffered Steiner Tree Construction C. Alpert G. Gandham S. Quay IBM Corp M. Hrkic Univ Illinois Chicago J. Hu Texas A&M Univ.
1 Timing-Driven, Over-the-Block Rectilinear Steiner Tree Construction with Pre-Buffering and Slew Constraints Yilin Zhang and David Z. Pan ECE, Univ. of.

1 Timing-Driven, Over-the-Block Rectilinear Steiner Tree Construction with Pre-Buffering and Slew Constraints Yilin Zhang and David Z. Pan ECE, Univ. of.
OCV-Aware Top-Level Clock Tree Optimization

OCV-Aware Top-Level Clock Tree Optimization
Advanced Interconnect Optimizations. Buffers Improve Slack RAT = 300 Delay = 350 Slack = -50 RAT = 700 Delay = 600 Slack = 100 RAT = 300 Delay = 250 Slack.

Advanced Interconnect Optimizations. Buffers Improve Slack RAT = 300 Delay = 350 Slack = -50 RAT = 700 Delay = 600 Slack = 100 RAT = 300 Delay = 250 Slack.
Cadence Design Systems, Inc. Why Interconnect Prediction Doesn’t Work.

Cadence Design Systems, Inc. Why Interconnect Prediction Doesn’t Work.
© imec 2004 1 Interconnect Width Selection for Deep Submicron Designs using the Table Lookup Method Mandeep Bamal*, Evelyn Grossar*, Michele Stucchi and.

© imec Interconnect Width Selection for Deep Submicron Designs using the Table Lookup Method Mandeep Bamal*, Evelyn Grossar*, Michele Stucchi and.
Ispd-2007 Repeater Insertion for Concurrent Setup and Hold Time Violations with Power-Delay Trade-Off Salim Chowdhury John Lillis Sun Microsystems University.

Ispd-2007 Repeater Insertion for Concurrent Setup and Hold Time Violations with Power-Delay Trade-Off Salim Chowdhury John Lillis Sun Microsystems University.
4/22/2015 1 Clock Network Synthesis Prof. Shiyan Hu Office: EREC 731.

4/22/ Clock Network Synthesis Prof. Shiyan Hu Office: EREC 731.
Topology-Aware Buffer Insertion and GPU-Based Massively Parallel Rerouting for ECO Timing Optimization Yen-Hung Lin, Yun-Jian Lo, Hian-Syun Tong, Wen-Hao.

Topology-Aware Buffer Insertion and GPU-Based Massively Parallel Rerouting for ECO Timing Optimization Yen-Hung Lin, Yun-Jian Lo, Hian-Syun Tong, Wen-Hao.
Buffer and FF Insertion Slides from Charles J. Alpert IBM Corp.

Buffer and FF Insertion Slides from Charles J. Alpert IBM Corp.
ELEN 468 Lecture 261 ELEN 468 Advanced Logic Design Lecture 26 Interconnect Timing Optimization.

ELEN 468 Lecture 261 ELEN 468 Advanced Logic Design Lecture 26 Interconnect Timing Optimization.
Confidentiality/date line: 13pt Arial Regular, white Maximum length: 1 line Information separated by vertical strokes, with two spaces on either side Disclaimer.

Confidentiality/date line: 13pt Arial Regular, white Maximum length: 1 line Information separated by vertical strokes, with two spaces on either side Disclaimer.
1 Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion Presented By Cesare Ferri Takumi Okamoto, Jason Kong.

1 Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion Presented By Cesare Ferri Takumi Okamoto, Jason Kong.
5/14/2015 1 Routing Prof. Shiyan Hu Office: EERC 731.

5/14/ Routing Prof. Shiyan Hu Office: EERC 731.
Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.

Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.
© Yamacraw, 2001 Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability A. Zelikovsky GSU Joint work with C. Alpert.

© Yamacraw, 2001 Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability A. Zelikovsky GSU Joint work with C. Alpert.
Low-power Clock Trees for CPUs Dong-Jin Lee, Myung-Chul Kim and Igor L. Markov Dept. of EECS, University of Michigan 1 ICCAD 2010, Dong-Jin Lee, University.

Low-power Clock Trees for CPUs Dong-Jin Lee, Myung-Chul Kim and Igor L. Markov Dept. of EECS, University of Michigan 1 ICCAD 2010, Dong-Jin Lee, University.
Minimum-Buffered Routing of Non- Critical Nets for Slew Rate and Reliability Control Supported by Cadence Design Systems, Inc. and the MARCO Gigascale.

Minimum-Buffered Routing of Non- Critical Nets for Slew Rate and Reliability Control Supported by Cadence Design Systems, Inc. and the MARCO Gigascale.
38 th Design Automation Conference, Las Vegas, June 19, 2001 Creating and Exploiting Flexibility in Steiner Trees Elaheh Bozorgzadeh, Ryan Kastner, Majid.

38 th Design Automation Conference, Las Vegas, June 19, 2001 Creating and Exploiting Flexibility in Steiner Trees Elaheh Bozorgzadeh, Ryan Kastner, Majid.
Interconnect Optimizations. A scaling primer Ideal process scaling: –Device geometries shrink by  = 0.7x) Device delay shrinks by  –Wire geometries.

Interconnect Optimizations. A scaling primer Ideal process scaling: –Device geometries shrink by  = 0.7x) Device delay shrinks by  –Wire geometries.

Similar presentations

Ads by Google