1. Impact of Gate-Length Biasing on Threshold-Voltage Selection Andrew B. Kahng ¶* Swamy Muddu * Puneet Sharma * CSE ¶ and ECE * Dept, Univ. of California San Diego

2. Outline Introduction Simultaneous V th Assignment and Gate-biasing Threshold Voltage Customization Experimental Setup Results Conclusions

3. Introduction Leakage significant portion of total power –High leakage short battery life Leakage variability Leakage reduction techniques –Standby leakage: MTCMOS, source biasing, input-vector control, transistor-stacks, etc. –Runtime leakage: V th assignment, gate-length biasing

4. Runtime Leakage Control V th assignment –High V th reduces I d sat (speed) and subthreshold leakage –Use low V th for timing critical devices, high V th for others –Obtained by different doping concentrations for each V th Increase in manufacturing costs Gate-length biasing [DAC04] –Increase gate-length of certain devices –Gate-length (L gate ) biasing reduces I d sat and subthreshold leakage –Bias only non-critical devices no deterioration in circuit speed –Leakage variability considerably reduced Change of leakage and delay (each normalized to 1) for an NMOS device in an industrial 130nm technology Impact on Leakage and Delay

5. Outline Motivation Simultaneous V th Assignment and Gate-biasing Threshold Voltage Customization Experimental Setup Results Conclusions

6. Simultaneous V th Assignment & Gate-Biasing Advantages of V th assignment –More favorable leakage-delay tradeoff –No increase in gate capacitance unlike biasing L gate biasing cannot be used as a replacement Advantages of L gate biasing –No additional process cost –Leakage variability reduction –Finer control over leakage-delay tradeoff V th assignment and L gate biasing can be used simultaneously This work: How does L gate biasing affect selection of V th s?

7. V th Selection Foundries select V th s that yield large leakage reductions in all designs For large leakage reduction: 1.Lot of cells must be assigned high V th 2.Large per-cell leakage reduction on assigning high V th Low V th determines circuit performance High V th determines power reduction –larger per-cell reduction increase high V th –larger #cells get high V th assigned decrease high V th optimum V th s should be determined by leakage-delay tradeoff and designs slack profile

8. Contributions Evaluate effectiveness of foundry-selected V th s –What is the best set of V th s? –Several other V th s used alternatively and leakage reductions estimated Estimate additional leakage reductions afforded due to L gate biasing –L gate biasing provides cost-effective leakage reduction Study impact of L gate biasing on best V th s –How does the set of best V th s changes when L gate biasing also available?

9. Outline Motivation Simultaneous V th Assignment and Gate-biasing Threshold Voltage Customization Experimental Setup Results Conclusions

10. Threshold Voltage Customization To study impact of changing foundry-set V th, artificially generate new V th –Modify VTH0 parameter in SVT SPICE model To test fidelity of new artificial V th –modify VTH0 of (foundry-set) SVT gradually –compare I off and I on characteristics with those of HVT / LVT Number of V th s limited by characterization runtime NameV th (volts) HHVT0.437 HVT0.402 HSVT0.362 SVT0.327 SLVT0.292 LVT0.257 LLVT0.222

11. Outline Motivation Simultaneous V th Assignment and Gate-biasing Threshold Voltage Customization Experimental Setup Results Conclusions

12. Experimental Setup VTH0 in 100nm device models modified to generate SPICE for four new V th s Library characterization done with Cadence SignalStorm v04.10 and Synopsys HSPICE –Sequential cells not touched (13 frequently occurring cells used) Three testcases (AES, DES3, OpenRisc1200) synthesized with Synopsys DC v2004.12 –Synthesis done iteratively with decreasing target clock cycle time to achieve tight slack distribution Leakage reduction obtained with a commercial optimizer tuned for V th assignment and L gate biasing Testcase# cellsLLVTLVTSLVT Delay (ns)Leakage (mW)Delay (ns)Leakage(mW)Delay (ns)Leakage (mW) AES220001.1349.461.2144.611.2942.24 OR1200370002.86024.012.96013.083.1107.69 DES3860001.08136.311.10618.081.1609.08

13. Outline Motivation Simultaneous V th Assignment and Gate-biasing Threshold Voltage Customization Experimental Setup Results Conclusions

14. Triple-V th vs. (Dual-V th + Biasing) Comparison of leakage reductions with triple-V th and dual-V th with biasing Triple-V th can reduce leakage by ~8% more than is possible with dual-V th Dual-Vth combined with biasing can achieve almost the same reduction

15. DES3 AES Modified Choice of Foundry V th s For foundry low-V th, HSVT yields lowest leakage power Foundry-set high-Vth may not yield best possible leakage reduction Reducing foundry set low-Vth does not result in leakage reduction For some designs, lowering low-Vth for some cells may result in creating slack on their fanout, which can then be used for high-Vth assignment (higher leakage reduction)

16. Vth Selection with Gate-Length Biasing For each (testcase, low V th ), change available L gate biases and identify optimum high V th Lower V th Max. BiasHigher Vth HHVTHVTHSVTSVT LLVTNo bias47.9451.3756.7861.58 4nm54.0757.2462.0964.88 6nm54.9757.9062.8465.50 8nm55.3558.2163.1065.79 10nm55.8758.4963.5066.06 LVTNo bias61.2764.0366.8365.89 4nm64.8966.6868.2368.35 6nm65.6667.3168.8569.19 8nm65.9767.7069.1269.72 10nm66.2167.9069.4670.15 SLVTNo bias64.4265.3363.2349.08 4nm67.1067.9366.4354.10 6nm67.7468.7267.2556.10 8nm68.0269.1067.8757.55 10nm68.2169.4168.3458.63 % leakage reduction for different high V th s with different gate biasing for AES

17. Outline Motivation Simultaneous V th Assignment and Gate-biasing Threshold Voltage Customization Experimental Setup Results Conclusions

18. Simultaneous L gate biasing and threshold-voltage assignment effective for runtime leakage control Experiments on large benchmarks with V th -L gate optimizer indicate comparable quality of results for triple-V th and dual- V th with L gate biasing ( a low-cost alternative ) Foundry V th s cannot always yield best possible leakage reduction –Analyze slack distribution, netlist structure, leakage-delay trade-off to choose or customize V th s Availability of L gate biasing has a small impact on choice of best high-V th –For well constrained design, best high-V th reduces in the presence of L gate biasing